Design and implementation of truncated multipliers for precision improvement

Devarani, R.; Manikandababu, C. S.

doi:10.1109/iccci.2013.6466244

Cited by 3 publications

(4 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In order to compare the efficiency of the proposed algorithm, the proposed method, the direct method, the Ref [7] method and the ref [9] method are respectively implemented on FPGA platform with Verlog-HDL. The FPGA platform is Xilinx XC4VLX15 that has rich interfaces and resources.…”

Section: Experimentation and Analysismentioning

confidence: 99%

“…When implementing it using direct method, floating number should be expanded to integer before operation, and should not use the DSP48 in the process of calculation; for the Ref [7] and Ref [9] method, configuration of compiler environment and implementation of programming respectively refer to the corresponding literatures; as to the method proposed in this paper, DSP48 is also not used in order to save computing resources of FPGA. Fig.…”

Section: Experimentation and Analysismentioning

confidence: 99%

“…Yet, a further enhancement is expected to save the memory resource. Shifting method [2,4,7,9] can convert the floating-point operations into fixed-point and addition operations. However, directly discarding the low bytes or the less significant partial products leads to the accumulation of errors.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Efficient RGB to YCbCr Color Space Conversion for Embedded Application

Jiang

Zhang

et al. 2014

AMM

View full text Add to dashboard Cite

Modern embedded portable devices usually have to deal with large amounts of video data. Due to massive floating-point multiplications, the color space conversion is inefficient on the embedded processor. Considering the characteristics of RGB to YCbCr color space conversion, this paper proposed a strategy for truncated-based LUT Multiplier (T-LUT Multiplier). On this base, an original approach converting RGB to YCbCr is presented which employs the T-LUT Multiplier and the pipeline-based adder. Experimental results demonstrate that the proposed method can obtain maximum operating frequency of 358MHz, 3.5 times faster than the direct method. Furthermore, the power consumption is less than that of the general method approximately by 15%~27%.

show abstract

Section: Experimentation and Analysismentioning

confidence: 99%

Section: Experimentation and Analysismentioning

confidence: 99%

See 1 more Smart Citation

Efficient RGB to YCbCr Color Space Conversion for Embedded Application

Jiang

Zhang

et al. 2014

AMM

View full text Add to dashboard Cite

show abstract

“…We are revisiting and comparing the different multipliers like cascade network, tree network, booth algorithm, pipelined architecture [8] and truncated structure [9]- [11] in this paper. From these multiplier structures we construct different filters and analyse its performance with a 4-point butterfly FFT [12].…”

Section: Design Simulation and Analysismentioning

confidence: 99%

Adaptive Algorithms Based Cross Talk Reduction Techniques Using Efficient Multipliers in VerilogHDL

Sivaraman¹,

Shukla²

2014

IJET

View full text Add to dashboard Cite

Abstract-Crosstalk is a phenomenon by which signals from one channel interfere with the signals of another. In this work, we have investigated the applications of cross talk elimination in interferometer, telecommunications, biomedicine, etc. to improve the performance in these areas. This paper discusses the various algorithms and techniques used to reduce cross talk with their trade-offs. A novel technique is proposed based on performance parameters of different multipliers and FFT method for the analysis of the said algorithms. The hardware utilization of a filter using truncated multiplier is efficient as there is a reduction of 73.64% in hardware with respect to FFT method while with normal cascade network multiplier the reduction is 83.87%.Index Terms-Adaptive filter, cross talk, fast block least mean square algorithm, fast block least mean square algorithm with distributed arithmetic, FFT, FIR Filter, least Mean square, multipliers. I. INTRODUCTIONCrosstalk is the phenomenon by which a signal transmitted on one circuit or channel creates an undesired effect in another circuit or channel as shown in Fig. 1. Crosstalk elimination is necessary to increase Signal to Noise Ratio (SNR). It is the undesired effect caused by coupling capacitance of the network. As technology is decreasing in size, we find it all the more important to keep interferences like crosstalk at bay. Main elimination techniques involve the phenomenon of digital filtering. Filtering can be either IIR or FIR. According to S. Hernandez-Montero etal [1], an FFT based technique is also proposed which tends to show high performance than linear phase digital filtering for high optimization of FPGA based interferometry which is used to measure the line electron density in plasmas. Adaptive filtering is another field which explores cross talk reduction using different Manuscript received February 11, 2014; revised May 20, 2014 [3]. A study of different multipliers is done as it contributes to the complexity of any filter structure. Based on the performance analysis of these different filters, the desired structure is used to construct the said above elimination techniques and tradeoffs will be observed.This paper discusses the review on crosstalk reduction techniques and algorithm in Section II while Section III gives an idea regarding design simulation and analysis. Section IV deals with the proposed structure for cross talk elimination and Section V concludes our paper. II. CROSSTALK REDUCTION TECHNIQUES AND ALGORITHMS: A REVIEWAccording to the various research papers, we are concerned with the different reduction techniques based on filtering and FFT. Let us analyse the above said reduction techniques and their dependence on the various parameters involved.A. FIR Filter FIR filter or Finite Impulse Response filter is a type of digital filter where the filter response to inputs are finite as it settles to zero after a finite amount of time. FIR filters are bounded-input bounded-output (BIBO) stables since output is a sum of finite number of fin...

show abstract

Formal Verification of Truncated Multipliers Using Algebraic Approach and Re-Synthesis

Yasin

et al. 2017

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

View full text Add to dashboard Cite

Design and implementation of truncated multipliers for precision improvement

Cited by 3 publications

References 14 publications

Efficient RGB to YCbCr Color Space Conversion for Embedded Application

Efficient RGB to YCbCr Color Space Conversion for Embedded Application

Adaptive Algorithms Based Cross Talk Reduction Techniques Using Efficient Multipliers in VerilogHDL

Formal Verification of Truncated Multipliers Using Algebraic Approach and Re-Synthesis

Contact Info

Product

Resources

About