A fully integrated 60-GHz transceiver for 802.11ad applications with superior performance in a 90-nm CMOS process versus prior arts is proposed and real based on a field-circuit co-design methodology. The reported transceiver monolithically integrates a receiver, transmitter, PLL Phase-Locked Loop) synthesizer, and LO (Local Oscillator) path based on a sliding-IF architecture. The transceiver supports up to a 16QAM modulation scheme and a data rate of 6 Gbit/s per channel, ZLWK DQ (90 (UURU 9HFWRU 0DJQLWXGH RI ORZHU WKDQ í G% 7KH UHFHLYHU SDWK DFKLHYHV D FRQ¿JXUDEOH FRQYHUVLRQ JDLQ RI a G% DQG D QRLVH ¿JXUH RI G% RYHU a *+] ZKLOH FRQVXPLQJ RQO\ P: RI SRZHU 7KH WUDQVPLWWHU DFKLHYHV D conversion gain of roughly 26 dB, with an output P 1dB RI G%P DQG D VDWXUDWHG RXWSXW SRZHU RI RYHU G%P FRQVXPLQJ mW of power from a 1.2-V supply. The LO path is composed of a 24-GHz PLL, doubler, and a divider chain, as well as an LO distribution network. In closed-loop operation mode, the PLL exhibits an integrated phase error of 3.3º rms (from 100 kHz to 100 MHz) over prescribed frequency bands, and a total power dissipation of only 26 mW. All measured results are rigorously loyal to the simulation.