Design aspects of a microprocessor data cache using 3D die interconnect technology

Reed, Paul; Yeung, Gus; Black, Bryan

doi:10.1109/icicdt.2005.1502578

Cited by 27 publications

(13 citation statements)

References 6 publications

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“…In this approach it is possible to implement a traditional microarchitecture across two or more die to construct a 3D floorplan. Such a Logic+Logic stacking, takes advantage of increased transistor density to eliminate wire between blocks of the microarchitecture [1][17] [25]. The result is shorter latencies between blocks yielding higher performance and lower power.…”

Section: Introduction To 3dmentioning

confidence: 99%

Die Stacking (3D) Microarchitecture

Black

Annavaram

Brekelbaum

et al. 2006

2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06)

497

284

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3D die stacking is an exciting new technology that increases transistor density by vertically integrating two or more die with a dense, high-speed interface. The result of 3D die stacking is a significant reduction of interconnect both within a die and across dies in a system. For instance, blocks within a microprocessor can be placed vertically on multiple die to reduce block to block wire distance, latency, and power. Disparate Si technologies can also be combined in a 3D die stack, such as DRAM stacked on a CPU, resulting in lower power higher BW and lower latency interfaces, without concern for technology integration into a single process flow. 3D has the potential to change processor design constraints by providing substantial power and performance benefits. Despite the promising advantages of 3D, there is significant concern for thermal impact. In this research, we study the performance advantages and thermal challenges of two forms of die stacking: Stacking a large DRAM or SRAM cache on a microprocessor and dividing a traditional microarchitecture between two die in a stack.Results: It is shown that a 32MB 3D stacked DRAM cache can reduce the cycles per memory access of a twothreaded RMS benchmark on average by 13% and as much as 55% while increasing the peak temperature by a negligible 0.08ºC. Off-die BW and power are also reduced by 66% on average. It is also shown that a 3D floorplan of a high performance microprocessor can simultaneously reduce power 15% and increase performance 15% with a small 14ºC increase in peak temperature. Voltage scaling can reach neutral thermals with a simultaneous 34% power reduction and 8% performance improvement.

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Section: Introduction To 3dmentioning

confidence: 99%

Die Stacking (3D) Microarchitecture

Black

Annavaram

Brekelbaum

et al. 2006

2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06)

497

284

View full text Add to dashboard Cite

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“…Each bank consists of a complete memory system (i.e., memory cell array, address decoder, write drivers, etc.). An overall reduction in wire length is obtained (about 50 % for certain configurations), resulting into significant reduction in both power and delay [16,18]. A 3D manufactured DRAM based on the stacking of banks manufactured by Samsung is described in [9].…”

Section: D Memory Architecturesmentioning

confidence: 99%

Yield Improvement for 3D Wafer-to-Wafer Stacked Memories

Taouil

Hamdioui

2012

J Electron Test

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Recent enhancements in process development enable the fabrication of three dimensional stacked ICs (3D-SICs) such as memories based on Wafer-to-Wafer (W2W) stacking. One of the major challenges facing W2W stacking is the low compound yield. This paper investigates compound yield improvement for W2W stacked memories using layer redundancy and compares it to wafer matching. First, an analytical model is provided to prove the added value of layer redundancy. Second, the impact of such a scheme on the manufacturing cost is evaluated. Third, these two parts are integrated to analyze the tradeoff between yield improvement and its associated cost; the realized yield improvement is also compared to yield gain obtained when using wafer matching. The simulation results show that for higher stack sizes layer redundancy realizes a significant yield improvement as compared to wafer matching, even at lower cost. For example, for a stack size of six stacked layers and a die yield of 85 %, a relative yield improvement of 118.79 % is obtained with two redundant layers, while this is 14.03 % only with wafer matching. The additional cost due to redundancy pays off; the cost of producing a good 3D stacked memory chip reduces with 37.68 % when using layer redundancy and only with 12.48 % when using wafer matching. Moreover, the results show that the benefits of layer redundancy become extremely significant for lower die yields. Finally, layer redundancy and wafer matching are integrated to obtain further cost reductions.

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“…Many have focused on improving single-core performance and power [2,7,26,44]. Some of this attention has focused on implementing a cache in 3D [25,29,40], even in the context of a multi-core NUCA layout [16]. Few studies have considered using additional dies entirely for SRAM or DRAM [2,17,18].…”

Section: Related Workmentioning

confidence: 99%