Design Considerations for Scalable High-Performance Vision Systems Embedded in Industrial Print Inspection Machines

Streaming warper with cubic spline interpolation for rectification of distorted images on FPGAs

“…The sWarper continues the series of building blocks presented in our publications on embedded real-time vision systems [7][8][9][10]. In the design process for high-performance vision systems it is necessary to match algorithms and architecture to each other [11].…”

“…Every channel carries 8-bit pixel data. Since several processing units need access to the SDRAM, a multi-port memory enables parallel operation of these units sharing the single SDRAM interface [9]. The conceptual idea is to stream data from the external memory through an imaging pipeline and then back to a (possibly different) memory location.…”

In-network processing based hardware acceleration for situational awareness

“…Low-level algorithms with a high degree of parallelism are a good fit for FPGAs, while higher-level algorithms involving branches and loops are better suited to DSPs. Weaknesses in one device may be compensated for by pairing it with a different type; for example, the combination of a DSP and FPGA to enable high performance vision systems [202].…”