Design considerations of CMOS active inductor for low power applications

Abstract

Previous studies have shown that transconductance-to-drain-current ratio based design technique is useful for optimizing analog circuits. In this paper, we explore challenges associated with designing a low-power active inductor. We focus in particular on sizing issues that arise as the transistor speed is maximized and the current consumption is minimized. Finally, we apply the results to design an amplifier integrated with an active inductor in 0.18 µm CMOS process and show that by systematically working through sizing issues, a 10 µA amplifier with a tunable range of 691 MHz and 1.05 GHz can be designed.

Evidence of Limitations of the Transconductance-to-Drain-Current Method (gm/Id) for Transistor Sizing in 28 nm UTBB FD-SOI Transistors

“…Therefore, case (b) is a compound of transistors of case (a), whereas case (c) is a single one but has a doubled width, W. For parallel transistors, case (b) can be treated as one merged transistor with a width of 2 W. Because the SOI transistor equations predict a bias current value that is proportional to W (ref. [10,11] and also because the PDK model of our technology uses charge-surface potentials, where the threshold voltage V TH does not depend on W), it is easy to conclude that all transistor cases are biased on the same g m /I d (see the detailed explanation in [5]). Therefore, on the basis of the previous geometrical argumentation of the compound transistor scheme when using the g m /I d method, and because of the transistor width (W) proportionality of some of their features, the following assumptions, which are the core figures of merit of the g m /I d method, are stated:…”

“…1. The unity gain frequency f T = 1 2π g m /C gg is expected to be independent of W, where C gg = C gs + C gb + C gd is the total gate capacitance [5]. 2.…”

“…2. The intrinsic gain, g m /g ds is expected to be independent of W [5]. 3. g m /g bs is expected to be independent of W [5].…”

“…First, utilizing simulations, we reviewed the compound transistor principle validity. We selected L = 180 nm for the study presented here because this gate channel length has been used and reported to be effective for CMOS circuits designs using the g m /I d method in many studies (for instance in [5]). Consequently, we maintained this transistor channel length value in our study for the sake of completeness and to better compare with other results.…”

“…It is accurate, is technology-independent and can be applied to more advanced CMOS technology, allowing the designer to implement current-independent sizing designs. The method is also adapted and can be used for a short channel length of L = 180 nm [4,5] and below [6]. Additionally, it is essential to emphasize that in the literature, it has been reported that many circuit designs based on the g m /I d design flow have achieved the desired specifications (it has been verified by simulations and measurements).…”