Design, Implementation, and Experimental Verification of 5 Gbps, 800 Mrad TID and SEU-Tolerant Optical Modulators Drivers

Ciarpi, Gabriele; Magazzù, G.; Palla, F.; Saponara, Sergio

doi:10.1109/tcsi.2019.2954755

Cited by 12 publications

(16 citation statements)

References 32 publications

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“…The current caused on a sensible node by an SEE can be modeled as a double exponential function [ 23 ] in Equation (5). In this work, the parameter model of Equation (6), which was taken from a previous high-frequency design we have done in the same technology [ 24 ], has been used:

where τ 1 and τ 2 are the constant times of the double exponential shape and Q is the charge released in the silicon substrate during a particle strike, which corresponds to a particle LET (Linear Energy Transfer) between 5 and 60 Mev∙cm 2 /mg.…”

Section: Simulation’s Resultsmentioning

confidence: 99%

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Analysis and Design of Integrated Blocks for a 6.25 GHz Spacefibre PLL

Mestice

Neri

Ciarpi

et al. 2020

Sensors

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The design of a Phase-Locked Loop (PLL) to generate the clock reference for the new Spacefibre standard is presented in this paper. Spacefibre has been recently released by the European Space Agency (ESA) and supports up to 6.25 Gbps for on-board satellite communications. Taking as a starting point a rad-hard 6.25 GHz Voltage Controlled Oscillator in 65 nm technology, this work presents the design of the key blocks for an integrated PLL: a Triple Modular Redundancy Phase/Frequency Detector, a Charge Pump, and a passive Loop Filter. The modeling activities carried out in an Advanced Design System have proven that the proposed PLL can be completely integrated on-chip, with a Loop Filter area consumption of only 6000 µm2 (considering the 65 nm technology). The design of active circuits has been carried out at the transistor level in a Cadence Virtuoso environment, implementing both system and layout rad-hard techniques, and different solutions are discussed in this paper. As a result, a compact (0.09 mm2), low power (10.24 mW), dead zone free and rad-hard PLL is obtained with a Phase Noise below −80 dBc/Hz @ 1 MHz. A preliminary block view and floor plan of the test chip is also proposed.

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Section: Simulation’s Resultsmentioning

confidence: 99%

“…As can be seen from the figure, the whole PLL occupies an area of about 0.09 mm 2 (the remaining area and pads are used for other designs not discussed in this paper). It is to be noted that the design of the pads is inherited from a previous design, where they were tested also with respect to resistance to radiation effects [ 24 ].…”

Section: Test Chipmentioning

confidence: 99%

Analysis and Design of Integrated Blocks for a 6.25 GHz Spacefibre PLL

Mestice

Neri

Ciarpi

et al. 2020

Sensors

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“…A 30% voltage amplitude degradation with respect to the pre-irradiation value was observed [17]. In addition, a single event upset (SEU) analysis of the same circuit was carried out in [44], proving its HEP-level radiation-tolerance.…”

Section: Samplesmentioning

confidence: 93%

“…Inductors (L p ) have been realized with a differential layout with a central tap to save area. Further details about the circuit design and purely electrical measurement results can be found in [44].…”

Section: Proposed Driver Designmentioning

confidence: 99%

Design and Performance Evaluation of Multi-Gb/s Silicon Photonics Transmitters for High Energy Physics

et al. 2020

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Optical links are rapidly becoming pervasive in the readout chains of particle physics detector systems. Silicon photonics (SiPh) stands as an attractive candidate to sustain the radiation levels foreseen in the next-generation experiments, while guaranteeing, at the same time, multi-Gb/s and energy-efficient data transmission. Integrated electronic drivers are needed to enable SiPh modulators’ deployment in compact on-detector front-end modules. A current-mode logic-based driver harnessing a pseudo-differential output stage is proposed in this work to drive different types of SiPh devices by means of the same circuit topology. The proposed driver, realized in a 65 nm bulk technology and already tested to behave properly up to an 8 MGy total ionizing dose, is hybridly integrated in this work with a lumped-element Mach–Zehnder modulator (MZM) and a ring modulator (RM), both fabricated in a 130 nm silicon-on-insulator (SOI) process. Bit-error-rate (BER) performances confirm the applicability of the selected architecture to either differential and single-ended loads. A 5 Gb/s data rate, in line with the current high energy physics requirements, is achieved in the RM case, while a packaging-related performance degradation is captured in the MZM-based system, confirming the importance of interconnection modeling.

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“…This work targets, as implementation technology, a commercial 65 nm CMOS from TSMC (Taiwan Semiconductor Manufacturing Company). This technology, thanks to its thin gate-oxide thickness, could be considered radiation hard up to few hundred Mrad TID levels, as proved in [ 5 ], and by us in previous designs of other high-speed circuits in [ 6 , 7 , 8 ]. To the best of the authors’ knowledge, in literature and market, there are not examples of rad-hard VCOs able to work at 6.25 GHz.…”

Section: Introductionmentioning

confidence: 88%

Analysis and Comparison of Rad-Hard Ring and LC-Tank Controlled Oscillators in 65 nm for SpaceFibre Applications

Monda

Ciarpi

Saponara

2020

Sensors

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This work presented a comparison between two Voltage Controlled Oscillators (VCOs) designed in 65 nm CMOS technology. The first architecture based on a Ring Oscillator (RO) was designed using three Current Mode Logic (CML) stages connected in a loop, while the second one was based on an LC-tank resonator. This analysis aimed to choose a VCO architecture able to be integrated into a rad-hard Phase Locked Loop. It had to meet the requirements of the SpaceFibre protocol, which supports frequencies up to 6.25 GHz, for space applications. The full custom schematic and layout designs are shown, and Single Event Effect simulations results, performed with a double exponential current pulses generator, are presented in detail for both VCOs. Although the RO-VCO performances in terms of technology scaling and high-integration density were attractive, the simulations on the process variations demonstrated its inability to generate the target frequency in harsh operating conditions. Instead, the LC-VCO highlighted a lower influence through Process-Voltage-Temperature simulations on the oscillation frequency. Both architectures were biased with a supply voltage of 1.2 V. The achieved results for the second architecture analyzed were attractive to address the requirements of the new SpaceFibre aerospace standard.

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Design, Implementation, and Experimental Verification of 5 Gbps, 800 Mrad TID and SEU-Tolerant Optical Modulators Drivers

Cited by 12 publications

References 32 publications

Analysis and Design of Integrated Blocks for a 6.25 GHz Spacefibre PLL

Analysis and Design of Integrated Blocks for a 6.25 GHz Spacefibre PLL

Design and Performance Evaluation of Multi-Gb/s Silicon Photonics Transmitters for High Energy Physics

Analysis and Comparison of Rad-Hard Ring and LC-Tank Controlled Oscillators in 65 nm for SpaceFibre Applications

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