Design methodologies for high-performance noise-tolerant XOR-XNOR circuits

Goel, S.; El-Gamel, Mohamed; Bayoumi, Magdy; Hanafy, Yasser Y.

doi:10.1109/tcsi.2005.860119

Cited by 73 publications

(22 citation statements)

References 22 publications

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“…Furthermore, the outputs of the circuit under test may be affected by noise. The noise amplitude level is usually ±5% of the supply voltage, i.e., 0.05 V in this study [12]. Hence, it will be assumed that any input vector producing an output voltage between 0.5 and 0.6 V for a specific fault cannot be used as a test vector for that fault because noise added to this output may toggle its digital value at the outputs of the inverters (front end of the test equipment).…”

Section: Testing Methodologymentioning

confidence: 99%

Current Mode Logic Testing of XOR/XNOR Circuit: A Case Study

Fouad¹,

Amer²,

Madian³

et al. 2013

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This paper investigates the issue of testing Current Mode Logic (CML) gates. A three-bit parity checker is used as a case study. It is first shown that, as expected, the stuck-at fault model is not appropriate for testing CML gates. It is then proved that switching the order in which inputs are applied to a gate will affect the minimum test set; this is not the case in conventional voltage mode gates. Both the circuit output and its inverse have to be monitored to reduce the size of the test set.

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Section: Testing Methodologymentioning

confidence: 99%

Current Mode Logic Testing of XOR/XNOR Circuit: A Case Study

Fouad¹,

Amer²,

Madian³

et al. 2013

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“…Apart from this, it can be observed that an efficient XOR circuit is required to perform the XORing of the two signals. This paper utilizes LP -XOR circuit presented in [11], [12] to implement the proposed design which consumes small amount of power (1.096 nW) to perform the XOR operation. As the introduced delay is in the order of picoseconds (92.35 ps), the XORed output produces pulses with the pulse duration in picoseconds.…”

Section: Proposed Trigger Pulse Generator Circuitmentioning

confidence: 99%

A Compact Low Power High Frequency Pulse Generator

Dwivedi

Mehra

Tyagi

et al. 2015

2015 Fifth International Conference on Communication Systems and Network Technologies

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This paper proposes a compact, low power high frequency trigger pulse generator circuit. Delay-introducing circuit that can incorporate a certain amount of delay during signal processing while maintaining the signal integrity is utilized in the proposed design. This paper evaluates performance of various delay-introducing circuits in terms of different design matrices. Further, this paper exploits the low power consuming delay element to implement the proposed trigger pulse generator. The proposed design generates very high frequency pulses at the cost of negligible power consumption. The effectiveness of the proposed circuit is presented by producing ultra-thin pulses of pulse duration 92.35 ps while consuming power of only 1.502 ȝw. Extensive simulations are carried out on SPICE @ 16-nm predictive technology model to verify the proposed design.

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“…4 is an optimized implementation for XOR function [9]. High functionality of PTL style is exploited here.…”

Section: Analysis Of Various Xor Gatementioning

confidence: 99%

Power - and variability-aware design of FinFET-based XOR circuit at nanoscale regime

Srivastava

Dwivedi

Islam

2014

2014 IEEE International Conference on Advanced Communications, Control and Computing Technologies

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Escalation in performance parameters due to CMOS technology scaling has proven its worth in the field of design and implementation. Integration density, low power dissipation and higher speed of operation are at their zenith level. This truculent towards technology scaling is now showing its adverse effect which is becoming a great concern from the researchers' point of view. Variability is one of the consequences of technology scaling.Equivalent to power, delay and area, variability also plays an important role in determining performance of circuits. This paper presents variability analysis of diverse exclusive-OR circuits in terms of average power and power-delay product (PDP) at the transistor level using 16-nm technology node. The investigation is supported by using simulation framework loaded with two nominal copies of the analogous XOR gate at both the ends -input and output. The intent of this note is to determine the circuit with minimal variability to PDP. Further, realization of the optimal XOR circuit is carried out by using emerging device namely Fin field effect transistor (FinFET). The propoundFinFET based realization of optimal XOR circuit offers 99.191 x improvement in PDP in contrast to its CMOS realization at nominal supply voltage ofVDD = 0.7 V.

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Design methodologies for high-performance noise-tolerant XOR-XNOR circuits

Cited by 73 publications

References 22 publications

Current Mode Logic Testing of XOR/XNOR Circuit: A Case Study

Current Mode Logic Testing of XOR/XNOR Circuit: A Case Study

A Compact Low Power High Frequency Pulse Generator

Power - and variability-aware design of FinFET-based XOR circuit at nanoscale regime

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