Design methodology for the IBM POWER7 microprocessor

Friedrich, Joshua; Puri, Ruchir; Brandt, Uwe; Buehler, Markus J.; DiLullo, Jack; Hopkins, Jeremy; Hossain, Mozammel; Kazda, Michael; Keinert, Joachim; Kurzum, Zahi M.; Lamb, Douglass; Lee, Alice; Musante, Frank; Noack, Jens; Osler, Peter J.; Posluszny, S.; Qian, Haifeng; Ramji, Shyam; Rao, Vasant B.; Reddy, L. J.; Ren, Haoxing; Rosser, Thomas; Russell, Benjamin R.; Sze, Cliff; Téllez, Gustavo

doi:10.1147/jrd.2011.2105692

Cited by 15 publications

(4 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…2 During the POWER6 and POWER7 time frame, improving custom design productivity was a major focus. These innovations allowed reducing the cost associated in custom design tasks in key areas, such as, automated leaf cell generation, placement, and routing [5], [8]. This focus on custom design productivity was quite appropriate at the time, seeing that custom design represented ~50% of the core macros and the majority of the most challenging macros.…”

Section: The Large Block Structured Synthesis (Lbss) Flowmentioning

confidence: 99%

“…Multiple synthesis scenarios are generated based on deviations from the initial design point. The high number of options available from the IBM PDSrtl synthesis tool [8] provides a vast design space unique for each macro. Modifying synthesis input settings, such as, logic restructuring, latch configurations, Vt assignments, wide wire assignments, are among others, produces a different design point in the design space.…”

Section: A Power Reduction and Macro Optimization By Design Space Exmentioning

confidence: 99%

See 1 more Smart Citation

POWER8 design methodology innovations for improving productivity and reducing power

Ziegler

Puri

Philhower

et al. 2014

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference

View full text Add to dashboard Cite

The design complexity of modern high performance processors calls for innovative design methodologies for achieving time-to-market goals. New design techniques are also needed to curtail power increases that inherently arise from ever increasing performance targets.This paper describes new design approaches employed by the POWER8 processor design team to address complexity and power consumption challenges. Improvements in productivity are attained by leveraging a new and more synthesis-centric design methodology. New optimization strategies for synthesized macros allow power reduction without sacrificing performance. These methodology innovations contributed to the industry leading performance of the POWER8 processor. Overall, POWER8 delivers a 2.5x increase in per-socket performance over its predecessor, POWER7+, while maintaining the same power dissipation.

show abstract

Section: The Large Block Structured Synthesis (Lbss) Flowmentioning

confidence: 99%

Section: A Power Reduction and Macro Optimization By Design Space Exmentioning

confidence: 99%

POWER8 design methodology innovations for improving productivity and reducing power

Ziegler

Puri

Philhower

et al. 2014

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference

View full text Add to dashboard Cite

show abstract

“…Most of the logic blocks in an IC are implemented using standard cell libraries and physical synthesis [1]. Interestingly, with technology scaling over the last decade, the fundamental standard cell layout architecture has not changed significantly.…”

Section: Introductionmentioning

confidence: 99%

Sub-20 nm design technology co-optimization for standard cell logic

Vaidyanathan¹,

Liebmann²,

Strojwas³

et al. 2014

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

View full text Add to dashboard Cite

Efficiency and manufacturability of standard cell logic is critical for an IC, as standard cells are at the heart of the nexus between technology definition, circuit design and physical synthesis. Conventional standard cell design techniques are increasingly ineffective as we scale to patterning restricted sub-20 nm CMOS nodes. To meet the constraints and leverage the features of future technology offerings, we propose a holistic design technology co-optimization (DTCO) for standard cell logic. In our holistic DTCO we co-optimize the standard cell architecture to balance manufacturability and efficiency at the cell level while taking into account block level considerations such as pin accessibility and power rail robustness. Our DTCO in a foundry 14 nm CMOS resulted in two standard cell architectures, namely, 10T_BiDir and 10T_UniDir. We evaluated these cell libraries with physically synthesized blocks and ring oscillator test structures in IBM 14SOI process. We observed that 10T_BiDir emerges as the preferred alternative at 14 nm CMOS, with 10T_UniDir promising better scalability to future nodes.

show abstract

“…During the POWER6 and POWER7 time frame, improving custom design productivity was a major focus. These innovations allowed reducing the cost associated in custom design tasks in key areas, such as, automated leaf cell generation, placement, and routing [12] [25]. This focus on custom design productivity was quite appropriate at the time, seeing that custom design represented 50% of the core macros and the majority of the most challenging macros.…”

Section: Introductionmentioning

confidence: 99%

Bridging high performance and low power in processor design

Puri

Choudhury

Qian

et al. 2014

Proceedings of the 2014 International Symposium on Low Power Electronics and Design

View full text Add to dashboard Cite

The design complexity of modern high performance processors calls for innovative design techniques and methodologies for achieving time-to-market goals. New design techniques are also needed to curtail power increases that inherently arise from ever increasing performance targets. This paper describes new processor design and optimization approaches that bridge the gap between high performance and low power. These techniques are flexible as they rely on automated synthesis-centric optimizations to enable power reduction without sacrificing performance. These methodology innovations contributed to the industry leading performance of the POWER8 processor.

show abstract

Design methodology for the IBM POWER7 microprocessor

Cited by 15 publications

References 7 publications

POWER8 design methodology innovations for improving productivity and reducing power

POWER8 design methodology innovations for improving productivity and reducing power

Sub-20 nm design technology co-optimization for standard cell logic

Bridging high performance and low power in processor design

Contact Info

Product

Resources

About