Design of a branch-based 64-bit carry-select adder in 0.18 μm partially depleted SOI CMOS

Abstract

The paper presents the design of a 64-bit carry-select adder in Branch-Based Logic, a static design style that minimizes the internal node capacitances. This feature is used to lower the dynamic power dissipation, while maintaining good speed performances. The experimental realization of the adder demonstrates an overall delay of 720 ps while only dissipating 96 mW at 1 GHz. The fabrication is based on the 0.18 µm IBM CMOS8S2 SOI technology, which uses partially depleted transistors and copper metallization.