Design of a Fast and Low-Power Sense Amplifier and Writing Circuit for High-Speed MRAM

Lee, Hochul; Alzate, Juan G.; Dorrance, Richard; Cai, Xue Qing; Marković, Dejan; Amiri, Pedram Khalili; Wang, Kang L.

doi:10.1109/tmag.2014.2367130

Cited by 21 publications

(4 citation statements)

References 21 publications

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“…With the given parameters in table 1 each coinflip requires 25 ns total for pulsing and relaxation, and draws on average 0.15 pJ of energy (the energy draw does not depend significantly on the weighting [9]). Assuming a 2 ns read stage [33] using a 10 mV Ohmic read, the total time for a single coinflip is 27 ns; the energy of the read is significantly less than the pulse and relax, and so is ignored. This calculation does not include the energy to generate the pulse, which will come from external CMOS circuitry.…”

Section: Applicationmentioning

confidence: 99%

Magnetic tunnel junction random number generators applied to dynamically tuned probability trees driven by spin orbit torque

Maicke,

Arzate,

Liu

et al. 2024

Nanotechnology

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Perpendicular magnetic tunnel junction (pMTJ)-based true-random number generators (RNG) can consume orders of magnitude less energy per bit than CMOS pseudo-RNG. Here, we numerically investigate with a macrospin Landau-Lifshitz-Gilbert equation solver the use of pMTJs driven by spin-orbit torque to directly sample numbers from arbitrary probability distributions with the help of a tunable probability tree. The tree operates by dynamically biasing sequences of pMTJ relaxation events, called ‘coinflips’, via an additional applied spin-transfer-torque current. Specifically, using a single, ideal pMTJ device we successfully draw integer samples on the interval [0,255] from an exponential distribution based on p-value distribution analysis. In order to investigate device-to-device variations, the thermal stability of the pMTJs are varied based on manufactured device data. It is found that while repeatedly using a varied device inhibits ability to recover the probability distribution, the device variations average out when considering the entire set of devices as a ‘bucket’ to agnostically draw random numbers from. Further, it is noted that the device variations most significantly impact the highest level of the probability tree, with diminishing errors at lower levels. The devices are then used to draw both uniformly and exponentially distributed numbers for the Monte Carlo computation of a problem from particle transport, showing excellent data fit with the analytical solution. Finally, the devices are benchmarked against CMOS and memristor RNG, showing faster bit generation and significantly lower energy usage.

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Section: Applicationmentioning

confidence: 99%

Magnetic tunnel junction random number generators applied to dynamically tuned probability trees driven by spin orbit torque

Maicke,

Arzate,

Liu

et al. 2024

Nanotechnology

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“…Based on this sense amplifier, different variants have been proposed in the literature to incorporate various functionalities such as reliability enhancement and offset cancellation. More works about sense amplifier designs for STT-MRAMs can be found in [99,101,102,[104][105][106][107].…”

Section: Voltage Developmentmentioning

confidence: 99%

Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions

Rao

Taouil

et al. 2021

2021 IEEE International Test Conference (ITC)

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“…Sensing and amplifying data signals are two important functions of a sense amplifier. However, the accuracy of sensing the data signals decreases with a decrease in the supply voltage [ 4 , 5 , 6 ]. As a result, a large number of memory cells are always busy loading a large number of bitlines, and consequently, the sensing delay increases drastically.…”

Section: Introductionmentioning

confidence: 99%

Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM Circuits

et al. 2023

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We live in a technologically advanced society where we all use semiconductor chips in the majority of our gadgets, and the basic criterion concerning data storage and memory is a small footprint and low power consumption. SRAM is a very important part of this and can be used to meet all the above criteria. In this study, LTSpice software is used to come up with a high-performance sense amplifier circuit for low-power SRAM applications. Throughout this research, various power reduction approaches were explored, and the optimal solution has been implemented in our own modified SRAM design. In this article, the effect of power consumption and the reaction time of the suggested sense amplifier were also examined by adjusting the width-to-length (W/L) ratio of the transistor, the power supply, and the nanoscale technology. The exact amount of power used and the number of transistors required by different approaches to better comprehend the ideal technique are also provided. Our proposed design of a low-power sense amplifier has shown promising results, and we employ three variations of VLSI power reduction techniques to improve efficiency. Low-power SRAMs embrace the future of memory-centric neuromorphic computing applications.

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Design of a Fast and Low-Power Sense Amplifier and Writing Circuit for High-Speed MRAM

Cited by 21 publications

References 21 publications

Magnetic tunnel junction random number generators applied to dynamically tuned probability trees driven by spin orbit torque

Magnetic tunnel junction random number generators applied to dynamically tuned probability trees driven by spin orbit torque

Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions

Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM Circuits

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