Design of AES S-box using combinational logic optimization

Design of Low Power and Secure Implementation of SBox and Inverse-SBox for AES

“…As AES calculation using components inside the GF (28), every component in the state exhibit connotes a byte with a worth that varies between 00H-FFH. The S-box has a settled size of 256 bytes spoke to as (16*16) bytes lattice [7]. SBOX is executed with various styles utilizing two regular methods: SubByte is non-straight change that utilizations 16 byte S-BOX.…”

An ultra-high throughput and fully pipelined implementation of AES algorithm on FPGA

“…Therefore in the proposed Com-Mux, we implement S-box based on the combinational logic circuit approach. In this implementation, the direct relation between inputs and output of S-box To solve this problem, we present a solution based on proposed method in [38]. In our solution, the truth In [38], these logic functions are considered as the inputs of a big 16 to 1 multiplexer (see Fig.…”

“…This method can reduce the area cost; however it suffers from unbreakable delay of memories that leads to a reduction in throughput. Finally in the last method, a simplification of the S-box truth table is employed using techniques such as SOP, 8 POS, 9 BDD, 10 PPRM 11 structure or its variance, and TBDD 12 [37,38]. Although this method provides a very high throughput but it suffers from extremely large area cost.…”

“…Hence in these papers, S-box is built by using reduced residue of prime numbers. A combinational logic design of S-box is presented in [38] where the architecture uses a boolean simplification of the truth table of S-box. Basic gates such as AND; NOT; OR and multiplexer are employed in this design.…”

An area-efficient design of reconfigurable S-box for parallel implementation of block ciphers

“…The S-box circuit is obtained from its truth table synthesis or generation rule when logic-based method is adopted. Although fewer resources are occupied by using two-level logic such as SOP, POS [4], PPRM [5] and BDD [6], or by employing logic circuit to achieve the calculation of the isomorphic fields of GF (2 8 ) (GF ((2 4 ) 2 ) [7] or GF (((2 2 ) 2 ) 2 ) [8]), the logic-base method provides little flexibility for different types of S-box operation. Furthermore, the accumulated resource of different S-box table synthesis should not be overlooked.…”