Design of an S-Band Nanowatt-Level Wakeup Receiver With Envelope Detector-First Architecture

Bassirian, Pouyan; Duvvuri, Divya; Liu, Ningxi; Truesdell, Daniel S.; Tsao, Han-Yu; Barker, N. Scott; Calhoun, Benton H.; Bowers, Steven M.

doi:10.1109/tmtt.2020.2987786

Cited by 15 publications

(13 citation statements)

References 29 publications

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“…The OVSF code is used in 3G wireless communication to minimize interference between different wireless channels [15]. An OVSF sequence of length L can 1) support L distinct addresses, with each sequence separated from another by L/2 bits; 2) correct up to max = L/4 − 1 − T bits, where T is an integer that can be adjusted digitally; and 3) be generated from an OVSF sequence of length L/2, as shown in (10).…”

Section: A Orthogonal Variable Spreading Factor Address Codementioning

confidence: 99%

“…H 2 is the inverse of H 2 . The shaded entries in (10) represent the non-distinguishable positions (N p ) and are occupied by bits shared between two OVSF sequences. The non-shaded entries in (10) represent the distinguishable positions (D p ) and are occupied by bits that distinguish two OVSF sequences.…”

Section: A Orthogonal Variable Spreading Factor Address Codementioning

confidence: 99%

“…s * i is s i with N e errors. N en is the number of errors that s * i has in N p (shaded elements in (10)) between s i and s j . N ed is the number of errors that s * i has in D p between s i and s j .…”

Section: B Detection Probabilitymentioning

confidence: 99%

“…The correlator circuit compares the address embedded in the beacon with that of the node and turns on the node if a match is found. The correlator can be implemented with an analog circuit [4], or a digital circuit requiring synchronization [3], [5]- [6], oversampling [7]- [10], or bit-level duty cycling [11]- [12].…”

Section: Introductionmentioning

confidence: 99%

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Analysis and Implementation of OVSF Address Decoders

Palmer

Hou

et al. 2022

IEEE Trans. Circuits Syst. II

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HAL is a multi-disciplinary open access archive for the deposit and dissemination of scientific research documents, whether they are published or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers. L'archive ouverte pluridisciplinaire HAL, est destinée au dépôt et à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d'enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

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Section: A Orthogonal Variable Spreading Factor Address Codementioning

confidence: 99%

Section: A Orthogonal Variable Spreading Factor Address Codementioning

confidence: 99%

Section: B Detection Probabilitymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Analysis and Implementation of OVSF Address Decoders

Palmer

Hou

et al. 2022

IEEE Trans. Circuits Syst. II

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“…A typical WuRx architecture is composed of two subsystems: an analog front-end (AFE) and a baseband logic. The AFE turns the RF input's OOK-modulated signal into a stream of bits, whereas the baseband logic generates the wake-up signal upon reception of the correct codeword [3][4][5][6][7][8][9]. State-of-the-art ultra-low-power WuRxs use oversampling techniques to overcome the phase alignment problem between the received data and internal clock and, with the aim of limiting the power consumption to a few nanowatts, typically use ring or relaxation oscillators.…”

Section: Introductionmentioning

confidence: 99%

A Gated Oscillator Clock and Data Recovery Circuit for Nanowatt Wake-Up and Data Receivers

et al. 2021

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This article presents a data-startable baseband logic featuring a gated oscillator clock and data recovery (GO-CDR) circuit for nanowatt wake-up and data receivers (WuRxs). At each data transition, the phase misalignment between the data coming from the analog front-end (AFE) and the clock is cleared by the GO-CDR circuit, thus allowing the reception of long data streams. Any free-running frequency mismatch between the GO and the bitrate does not limit the number of receivable bits, but only the maximum number of equal consecutive bits (Nm). To overcome this limitation, the proposed system includes a frequency calibration circuit, which reduces the frequency mismatch to ±0.5%, thus enabling the WuRx to be used with different encoding techniques up to Nm = 100. A full WuRx prototype, including an always-on clockless AFE operating in subthreshold, was fabricated with STMicroelectronics 90 nm BCD technology. The WuRx is supplied with 0.6 V, and the power consumption, excluding the calibration circuit, is 12.8 nW during the rest state and 17 nW at a 1 kbps data rate. With a 1 kbps On-Off Keying (OOK) modulated input and −35 dBm of input RF power after the input matching network (IMN), a 10−3 missed detection rate with a 0 bit error tolerance is measured, transmitting 63 bit packets with the Nm ranging from 1 to 63. The total sensitivity, including the estimated IMN gain at 100 MHz and 433 MHz, is −59.8 dBm and −52.3 dBm, respectively. In comparison with an ideal CDR, the degradation of the sensitivity due to the GO-CDR is 1.25 dBm. False alarm rate measurements lasting 24 h revealed zero overall false wake-ups.

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Communication Protocol Optimization of Electric Low Power Wireless Sensor Network Based on Active Wakeup

An,

Huang

2023

Lecture Notes in Electrical Engineering

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Design of an S-Band Nanowatt-Level Wakeup Receiver With Envelope Detector-First Architecture

Cited by 15 publications

References 29 publications

Analysis and Implementation of OVSF Address Decoders

Analysis and Implementation of OVSF Address Decoders

A Gated Oscillator Clock and Data Recovery Circuit for Nanowatt Wake-Up and Data Receivers

Communication Protocol Optimization of Electric Low Power Wireless Sensor Network Based on Active Wakeup

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