Design of band-gap engineered silicon-germanium Junctionless Double-gate FET for ZRAM application

Sinha, Dheeraj Kumar; Chatterjee, Amitabh; Trivedi, Gaurav; Koldyaev, Victor

doi:10.1109/codec.2015.7893195

Cited by 2 publications

(1 citation statement)

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“…In the past ten years, various device structures attempting to overcome the RT degradation due to silicon film thickness downscaling such as ZRAM, A 2 RAM, and feedback field-effect transistor (FBFET) were proposed for the 1 T DRAM. [11][12][13][14][15] Among various transistor structures, tunneling and FBFETs have attracted attention due to their low gate voltage operation and outstanding switching characteristics. [16][17][18][19][20][21] The switching characteristics of FBFET can contribute to high current ratio characteristics when the device is applied to 1 T DRAM.…”

Section: Introductionmentioning

confidence: 99%

Reliability improvement of 1T DRAM based on feedback transistor by using local partial insulators

Jang

Ansari

Kım

et al. 2021

Jpn. J. Appl. Phys.

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This paper proposes a one-transistor dynamic random-access memory (1 T DRAM) with local partial insulator (LPI) to increase data retention time. Proposed 1 T DRAM cell has improved retention characteristics because LPIs inhibit stored carrier movement with a high energy barrier. Definition of retention time in the proposed 1 T DRAM is introduced at hold “0” state. Device optimization with parameter variation is investigated with device simulation. As the barrier length increases, retention characteristics can be improved but it also causes a decrease in the I1/I0 current ratio. An increase in LPI length can improve the retention characteristics but reduce the I1/I0 current ratio. It was confirmed that the retention characteristics were improved as the hold bias was decreased. Finally, the retention characteristics were optimized when the LPI was precisely formed at the junction boundary.

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