Design of CMOS three-stage amplifiers for fast-settling switched-capacitor circuits

Golabi, Sajad; Yavari, Mohammad

doi:10.1007/s10470-014-0332-y

Cited by 11 publications

(4 citation statements)

References 25 publications

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“…Such options are not available for high-linearity applications since in those cases, a pseudo-differential intermediate stage is used to improve signal swing and reduce distortion. The authors of [7] implemented a two-loop switched-capacitor solution but do not go into details concerning the trade-offs involved in the design of those CMFB loops. Some authors have even achieved the impressive feat of designing four-stage fully differential amplifiers with a single CMFB loop [4,8], but their approaches rely on the common-mode error amplifier pole being at a much higher frequency than the differential loop bandwidth, which may not be feasible in low-power amplifiers or high-frequency applications.…”

Section: Introductionmentioning

confidence: 99%

Design Trade-Offs in Common-Mode Feedback Implementations for Highly Linear Three-Stage Operational Transconductance Amplifiers

et al. 2021

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Fully differential amplifiers require the use of common-mode feedback (CMFB) circuits to properly set the amplifier’s operating point. Due to scaling trends in CMOS technology, modern amplifiers increasingly rely on cascading more than two stages to achieve sufficient gain. With multiple gain stages, different topologies for implementing CMFB are possible, whether using a single CMFB loop or multiple ones. However, the impact on performance of each CMFB approach has seldom been studied in the literature. The aim of this work is to guide the choice of the CMFB implementation topology evaluating performance in terms of stability, linearity, noise and common-mode rejection. We present a detailed theoretical analysis, comparing the relative performance of two CMFB configurations for 3-stage OTA topologies in an implementation-agnostic manner. Our analysis is then corroborated through a case study with full simulation results comparing the two topologies at the transistor level and confirming the theoretical intuition. An active-RC filter is used as an example of a high-linearity OTA application, highlighting a 6 dB improvement in P1dB in the multi-loop implementation with respect to the single-loop case.

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Section: Introductionmentioning

confidence: 99%

Design Trade-Offs in Common-Mode Feedback Implementations for Highly Linear Three-Stage Operational Transconductance Amplifiers

et al. 2021

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“…Therefore, the settling behavior modeling, analysis and settling time evaluation for these amplifiers have remained to be an attractive research issue over the years [1][2][3][4][5][6][7][8][9][10][11]. Recently, because of the high-speed and high-precision requirements in discretetime applications driven by the relentless shrinking of the process technology, considerable attentions have been devoted to the settling time oriented design of such amplifiers in literature [12][13][14][15][16][17][18].…”

Section: Introductionmentioning

confidence: 99%

“…Most of them rely on the analytical relationships between the settling time and the parameters such as the slewing rate, the bandwidth and the phase margin, the poles and zeros or the damping factor. Some approaches further employ numerical optimization for the simultaneous considerations of other design objectives [15,16]. This paper addresses the settling time design of the classical CMOS two-stage Miller compensated operational amplifiers as shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

Exact design for the settling time of two-stage Miller compensated operational amplifiers

Yu-shun

2021

Analog Integr Circ Sig Process

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Most of the currently existed settling time design methods for the Miller-compensated two-stage operational amplifiers are based on the approximate analytical model and can obtain only inaccurate results. This paper presents an approach for the exact settling time design for this widely used circuit. By the compensation of the errors in the analytical settling behavior model and executing the conventional design procedure repeatedly, an iterative design scheme is developed. The overall errors are removed by the exact performance computation with the SPICE simulation and the accurate MOS model based sizing in the entire design process. Taking advantage of the fast convergence and precision feature of this method, an efficient process variation-aware design algorithm is further presented. Simulated design results for the amplifiers in 0.18 lm and 90 nm technology are provided to illustrate the effectiveness of the proposed method.

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“…There are several publications considering the optimization of settling performance in the design of multistage OTAs [7][8][9][10][11][12][13][14]. These publications have been aimed to improve the linear settling time by its optimization using systematic design methodologies.…”

Section: Introductionmentioning

confidence: 99%

A three-stage class AB operational amplifier with enhanced slew rate for switched-capacitor circuits

Golabi

Yavari

2015

Analog Integr Circ Sig Process

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In this paper, a three-stage class AB operational transconductance amplifier (OTA) with large slew rate is presented. The reversed nested Miller compensation technique is used to stabilize the proposed OTA, allowing the slew rate enhancement to be achieved by using class AB input and output stages. A flipped-voltage follower cell in the first stage in combination with a switched-capacitor level shifter in the last stage are utilized to implement the class AB operation. Circuit level simulation results are provided using HSPICE and a 90 nm CMOS technology which show 306 % enhancement in the large-signal FoM with approximately the same power dissipation compared to the class A OTA. The achieved settling time with 0.02 % accuracy for the proposed class AB and conventional class A OTAs are 7.5 and 15.3 ns, respectively.

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Design of CMOS three-stage amplifiers for fast-settling switched-capacitor circuits

Cited by 11 publications

References 25 publications

Design Trade-Offs in Common-Mode Feedback Implementations for Highly Linear Three-Stage Operational Transconductance Amplifiers

Design Trade-Offs in Common-Mode Feedback Implementations for Highly Linear Three-Stage Operational Transconductance Amplifiers

Exact design for the settling time of two-stage Miller compensated operational amplifiers

A three-stage class AB operational amplifier with enhanced slew rate for switched-capacitor circuits

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