Design of Crystal-Oscillator Frequency Quadrupler for Low-Jitter Clock Multipliers

Megawer, Karim M.; Elkholy, Ahmed; Ahmed, Mostafa Gamal; Elmallah, Ahmed; Hanumolu, Pavan Kumar

doi:10.1109/jssc.2018.2872539

Cited by 25 publications

(4 citation statements)

References 15 publications

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“…Transistor frequency multipliers have good unidirectional, isolation and gain. The power of the frequency multiplier is inversely proportional to the square of octave frequency, and the octave frequency cannot be too high, generally 2-3 times [18], [19].…”

Section: Traditional Frequency Multiplication Methodsmentioning

confidence: 99%

A Frequency Multiplication Method Based on Extracting Harmonic From Narrow Pulse

Tang

Wang

et al. 2019

IEEE Access

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Frequency multiplier is a nonlinear circuit that can realize frequency multiplication of input signal with wide application in communication, navigation, radar, and other fields. This paper proposes a frequency multiplication method based on extracting harmonic from a narrow pulse. Then, in accordance with this means, it develops a ten times frequency multiplier, finally achieving frequency multiplication taking the rubidium atomic frequency standard as a reference. The frequency multiplier possesses some features of high-efficient multiplication, low noise floor, simple structure, easy implementation, and cheaper cost. Based on the experimental results, if PRS10, the rubidium atomic frequency standard, is regarded as a reference, the noise floor of frequency multiplier is superior to 1.60E − 12/s. Additionally, the relative frequency error of the output ten times the frequency multiplication signal (100 MHz) is less than 8.00E − 12.

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Section: Traditional Frequency Multiplication Methodsmentioning

confidence: 99%

A Frequency Multiplication Method Based on Extracting Harmonic From Narrow Pulse

Tang

Wang

et al. 2019

IEEE Access

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“…By doing so, the quantization noise is shaped to a higher frequency and can be filtered out even with a wide loop bandwidth. A simple way to do this is to multiply the reference frequency by an integer value using a reference multiplier [22], [23], [24]. Although Fig.…”

Section: B Increasing the Noise Shaping Frequencymentioning

confidence: 99%

A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual-Feedback and Split-Feedback Frequency Division With Phase-Domain Filtering

Osada,

Xu,

Yang

et al. 2024

IEEE J. Solid-State Circuits

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A phase-locked loop (PLL) employing a split-feedback divider and nested-PLL-based phase-domain low-pass filter (PDLPF) within the harmonic-mixer (HM)-based dual-feedback architecture is presented in this article. The proposed architecture not only overcomes the noise shaping frequency limitation seen in a conventional dual-feedback PLL, but also solves stability and noise overhead issues that were present in the prior art. Due to the wide loop bandwidth that can be achieved because of the effective quantization noise suppression by the proposed method, the fractional-N synthesizer is realized with low phase noise and jitter using only ring voltage-controlled oscillator (VCO), allowing an implementation that is low area and robust to magnetic coupling compared with ones using LC-VCOs. A proof of concept prototype is implemented in 65-nm CMOS technology that achieves a −229.4-dB jitter-power figure-of-merit (FoM) and −49-dBc worst-case fractional spurs with a 40-MHz reference.

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“…To further suppress the DCO noise by means of increasing the loop bandwidth, a reference doubler/quadrupler can be employed to increase the effective PD rate [7], [8], but this would require additional low-noise circuitry and calibration logic in the reference path.…”

Section: B Reference-waveform Sampling/oversampling Techniquesmentioning

confidence: 99%

“…To alleviate this issue, a digital-to-time converter (DTC) was introduced to reduce the required range of high-resolution TDCs [2]- [5]. Aiming to push the jitter performance without resorting to high-frequency, but high-cost, crystal oscillators, solutions with inexpensive crystal oscillators at ≤50 MHz, but in a collaboration with a reference doubler or quadrupler, were proposed in [3], [6], [7], and [8]. However, that increases the circuit complexity and necessitates additional delay lines or DACs for duty-cycle calibrations.…”

mentioning

confidence: 99%

A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL

Siriburanon

et al. 2021

IEEE J. Solid-State Circuits

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This article presents a low-power fractional-N alldigital phase-locked loop (ADPLL) employing a referencewaveform oversampling (ROS) phase detector (PD) that increases its effective rate four times, thus leading to lower jitter and settling time. The proposed ROS-PD adopts a bottom-plate sampling with a voltage zero-forcing technique, which yields high power efficiency and supports fractional phase compensation in the voltage domain through a programmable DAC. The PD output is then amplified by a low-noise gated amplifier and digitized by a low-power successive approximation register analog-todigital converter (SAR-ADC). Leveraging the benefits of digital architecture, gain mismatches from the waveform estimator are calibrated by means of an LMS algorithm, consequently lowering fractional spurs. The proposed ADPLL is implemented in TSMC 28-nm LP CMOS. The prototype generates a 2.0-2.3-GHz carrier with an rms jitter of 414 fs while consuming only 1.15 mW. This corresponds to a state-of-the-art ADPLL FoM jitter of −247 dB in a fractional-N mode. Due to the wide (largely linear) monotonic range and 4× oversampling rate from a 50-MHz reference, without any additional circuitry, the proposed ADPLL can settle within 3 µs in face of a 70-MHz frequency step.

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Design of Crystal-Oscillator Frequency Quadrupler for Low-Jitter Clock Multipliers

Cited by 25 publications

References 15 publications

A Frequency Multiplication Method Based on Extracting Harmonic From Narrow Pulse

A Frequency Multiplication Method Based on Extracting Harmonic From Narrow Pulse

A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual-Feedback and Split-Feedback Frequency Division With Phase-Domain Filtering

A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL

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