Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool

Aksoy, Levent; Lazzari, Cristiano; Costa, Eduardo; Flores, Paulo; Monteiro, José

doi:10.1109/tvlsi.2012.2188917

Cited by 26 publications

(7 citation statements)

References 25 publications

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“…Aksoy et al [9] have represented the design of low complexity using bit-parallel MCM operation which reduces the complexity of many DSP systems. In digital-serial design, input data are divided into the number of bits.…”

Section: Literature Surveymentioning

confidence: 99%

Efficient Finite Impulse Response Filter Architecture Using Multiple Constant Multiplication and Common Sub-Expression Elimination Techniques

Shukla

Beulet

2017

Asian J Pharm Clin Res

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Objective: This paper introduces the computationally efficient, low power, high speed partial reconfigurable Finite impulse response (FIR) filter design using multiple constant multiplication technique (MCM). The complexity of many digital signal processing (DSP) systems is reduced by multiple constant multiplication operation.Methods: Multiple constant multiplications (MCM) along with methods like common sub expression elimination (CSE) is used for the better performance of digital signal processing systems. This paper introduces a CSE operation of finite Impulse response filter design which is solved with decreased number of operators.Results: Using these techniques shows that the area efficiency is increased when compared with designs based on direct form implementation of FIR filters. Conclusion:This method has achieved minimum area and delay with a high process rate. The future work will be for using CSE for 0-1 ILP.

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Section: Literature Surveymentioning

confidence: 99%

Efficient Finite Impulse Response Filter Architecture Using Multiple Constant Multiplication and Common Sub-Expression Elimination Techniques

Shukla

Beulet

2017

Asian J Pharm Clin Res

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“…The multiplier block of the digital FIR filter in its transposed form is shown, where the multiplication of filter coefficients with the filter input is realized and it has significant impact on the complexity and performance of the design because a large number of constant multiplications are required [11], [15] . Hence, the multiplication of filter coefficients with the input data is implemented under shift-adds architecture, where each constant multiplication is realized using addition/subtraction and shift operations [17].…”

Section: Mcm-shift-add Techniquesmentioning

confidence: 99%

To Develop and Implement Low Power High Speed VLSI for Processing Signals using Multirate Techniques

Rajendra¹

2015

IJRITCC

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Abstract:-Multirate technique is necessary for systems with different input and output sampling rates. Recent advances in mobile computing and communication applications demand low power and high speed VLSI DSP systems [4]. This Paper presents Multirate modules used for filtering to provide signal processing in wireless communication system. Many architecture developed for the design of low complexity, bit parallel Multiple Constant Multiplications operation which dominates the complexity of DSP systems. However, major drawbacks of present approaches are either too costly or not efficient enough. On the other hand, MCM and digit-serial adder offer alternative low complexity designs, since digit-serial architecture occupy less area and are independent of the data word length [1] [10]. Multiple Constant Multiplications is efficient way to reduce the number of addition and subtraction in polyphase filter implementation. This Multirate design methodology is systematic and applicable to many problems. In this paper, attention has given to the MCM & digit serial architecture with shifting and adding techniques that offers alternative low complexity in operations. This paper also focused on Multirate Signal Processing Modules using Voltage and Technology scaling. Reduction of power consumption is important for VLSI system and also it becomes one of the most critical design parameter. Transistorized Multirate module which has full custom design with different circuit topology and optimization level simulated on cadence platform. Multirate modules are used AMI 0.6 um, TSMC 0.35 um, and TSMC 0.25 um technologies for different voltage scaling. The presented methodology provides a systematic way to derive circuit technique for high speed operation at a low supply voltage. Multirate polyphase interpolator and decimator are also designed and optimized at architectural level in order to analyze the terms power consumption, area and speed.

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“…Based on this algorithm an n-dimensional Reduced Shift and Add Graph (RSAG-n) algorithm [13] has been developed, that reduces the adder cost and also the number of shifts. This algorithm has an increased adder cost, which will be dominating for larger digit-sizes.…”

Section: Rsag-n Algorithmmentioning

confidence: 99%

Performance evaluation of FIR filters using digit serial architectures

Kumar¹,

Teja²

2015

2015 International Conference on Microwave, Optical and Communication Engineering (ICMOCE)

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In FIR Filter design many architectures and algorithms been proposed for the design of low complexity parallel and serial Multiple Constant Multiplication (MCM) operation. MCM is one of the way to implement several constant variable multiplications with input data using adders, subtractor and shifters. But these designs cannot achieve tradeoff between area, delay and power. The digit serial MCM design can be one of the alternatives to implement MCM. By varying the digit size better results can be achieved. In this paper, the problem of reducing the gate level area in digit serial MCM design architectures with optimization algorithms and digit size variation effect is also studied. Operational results show the competence of the algorithm and digit serial architecture in the design of MCM and finite impulse response filter.

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Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool

Cited by 26 publications

References 25 publications

Efficient Finite Impulse Response Filter Architecture Using Multiple Constant Multiplication and Common Sub-Expression Elimination Techniques

Efficient Finite Impulse Response Filter Architecture Using Multiple Constant Multiplication and Common Sub-Expression Elimination Techniques

To Develop and Implement Low Power High Speed VLSI for Processing Signals using Multirate Techniques

Performance evaluation of FIR filters using digit serial architectures

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