Design of High-Performance Microprocessor Circuits

Abstract

This book covers the design of next generation microprocessors in deep submicron CMOS technologies. The chapters in Design of High Performance Microprocessor Circuits were written by some of the world's leading technologists, designers, and researchers. All levels of system abstraction are covered, but the emphasis rests squarely on circuit design. Examples are drawn from processors designed at AMD, Digital/Compaq, IBM, Intel, MIPS, Mitsubishi, and Motorola.

Novel Eight-Transistor SRAM cell for write power reduction

“…This is known as stack effect. Stacking of transistors is an effective way to reduce the subthreshold leakage current [5]. In 1 → 0/0 → 1 write patterns, power consumption is reduced due to absence of discharging activity at bitline (Table I (b)).…”

“…Over the years, SRAM has undergone tremendous advancement [3,4]. Low power design techniques [5,6] are based on reducing the voltage swing level and capacitance. SRAM cells include both read and write operations.…”

Near-optimal precharging in high-performance nanoscale CMOS caches

“…Bitline precharging is achieved through either clocked precharging that clocks the precharge devices every cycle or static pull-up that statically leaves them on all the time [5]. Static pull-up has the advantage that it does not require a heavily loaded precharge clock signal.…”

“…To reduce the bitline capacitive load and achieve faster access times, these caches are divided into multiple subarrays of SRAM cell rows. To hide bitline precharging time and minimize cache access latency, these caches typically pull up the bitlines in all subarrays statically or on every clock cycle [5]. Unfortunately, such aggressive and blind bitline precharging results in a significant energy discharge through the bitlines even in unaccessed subarrays.…”

Modeling of coplanar waveguide for buffered clock tree

“…As semiconductor technology scales to smaller feature sizes, leakage power increases exponentially because transistor threshold voltages are reduced in concert with supply voltage to maintain transistor performance. For current high-performance design methodologies, the contribution of leakage power increases at each technology generation [1]. The Intel Pentium IV processors running at 3GHz already have an almost equal amount of leakage and dynamic power [2].…”