Design of Hybrid Second-Level Caches

Valero, Alejandro; Sahuquillo, Julio; Petit, Salvador; López, Pedro; Duato, J.

doi:10.1109/tc.2014.2346185

Cited by 14 publications

(12 citation statements)

References 37 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Recent studies [8], [9] have proposed hybrid architectures, wherein the SRAM is integrated with NVMs to use advantages of both technologies. Energy consumption is still a primary concern in embedded systems since they are limited by battery constraint.…”

Section: Related Workmentioning

confidence: 99%

Notice of Violation of IEEE Publication Principles: A heterogeneous memory organization with minimum energy consumption in 3D chip-multiprocessors

Asad

Onsori

Jahed‐Motlagh

et al. 2016

2016 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)

View full text Add to dashboard Cite

Abstract-Main memories play an important role in overall energy consumption of embedded systems. Using conventional memory technologies in future designs in nanoscale era cause a drastic increase in leakage power consumption and temperaturerelated problems. Emerging non-volatile memory (NVM) technologies offer many desirable characteristics such as nearzero leakage power, high density and non-volatility. They can significantly mitigate the issue of memory leakage power in future embedded chip-multiprocessor (eCMP) systems. However, they suffer from challenges such as limited write endurance and high write energy consumption which restrict them for adoption in modern memory systems. In this article, we propose a stacked hybrid memory system for 3D chip-multiprocessors to take advantages of both traditional and non-volatile memory technologies. For reaching this target, we present a convex optimization-based model that minimizes the system energy consumption while satisfy endurance constraint in order to design a reliable memory system. Experimental results show that the proposed method improves energy-delay product (EDP) and performance by about 44.8% and 13.8% on average respectively compared with the traditional memory design where single technology is used.

show abstract

Section: Related Workmentioning

confidence: 99%

Notice of Violation of IEEE Publication Principles: A heterogeneous memory organization with minimum energy consumption in 3D chip-multiprocessors

Asad

Onsori

Jahed‐Motlagh

et al. 2016

2016 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)

View full text Add to dashboard Cite

show abstract

“…1 (b), the eDRAM cells are arranged in a two-dimensional array whereby each storage capacitor is connected to the bitline wire through the access transistor. Even though the employment of capacitor for maintaining the logic value has significantly saved the area compared to the SRAM utilizing 6 transistors per bit cell, the eDRAM technology suffers from high dynamic energy consumption due to mandatory periodic refresh required to keep the stored value in the valid state [19]. It has been reported in [20] that refresh scheme contributes around 70% to the overall energy consumption in LLC.…”

Section: Background On Technology Trends For Cache Organizationmentioning

confidence: 99%

Read-Tuned STT-RAM and eDRAM Cache Hierarchies for Throughput and Energy Optimization

Khoshavi

DeMara

2018

IEEE Access

View full text Add to dashboard Cite

As capacity and complexity of on-chip cache memory hierarchy increases, the service cost to the critical loads from Last Level Cache (LLC), which are frequently repeated, has become a major concern. The processor may stall for a considerable interval while waiting to access the data stored in the cache blocks in LLC, if there are no independent instructions to execute. To provide accelerated service to the critical loads requests from LLC, this work concentrates on leveraging the additional capacity offered by replacing SRAM-based L2 with Spin-Transfer Torque Random Access Memory (STT-RAM) to accommodate frequently accessed cache blocks in exclusive read mode in favor of reducing the overall read service time. Our proposed technique partitions L2 cache into two STT-RAM arrangements with different write performance and data retention time. The retentionrelaxed STT-RAM arrays are utilized to effectively deal with the regular L2 cache requests while the high retention STT-RAM arrays in L2 are selected for maintaining repeatedly read accessed cache blocks from LLC by incurring negligible energy consumption for data retention. Our experimental results show that the proposed technique can reduce the mean L2 read miss ratio by 51.4% and increase the IPC by 11.7% on average across PARSEC benchmark suite while significantly decreasing the total L2 energy consumption compared to conventional SRAMbased L2 design.

show abstract

“…The results of the experiments show that the hybrid cache improves performance by 5.9% on average and the total energy consumption is reduced by 32%. Valero et al [85] designed a hybrid cache architecture with data encoding using low cost peripheral circuitry to improve energy, latency and endurance of cache simultaneously. The technique splits the input data between the STT-RAM and SRAM caches per the proportion of ones in input data.…”

Section: Dynamic and Leakage Energy Saving Techniquesmentioning

confidence: 99%

“…The recent advancements of multicore and multithreading technologies have seen the CPU processing power having a great growth [85] caused by the advancements in fabrication technologies, modern chip designs with more and smaller transistors embedded in it. The reduced transistor size offers a lesser dynamic energy for switching at the cost of higher static energy because of leakage while the performance improvement of storage systems has lagged.…”

Section: Introductionmentioning

confidence: 99%

A Survey of Emerging Architectural Techniques for Improving Cache Energy Consumption

Bhebhe

Agyeman

2016

CAE

View full text Add to dashboard Cite

Abstract-The search goes on for another ground breaking phenomenon to reduce the ever-increasing disparity between the CPU performance and storage. There are encouraging breakthroughs in enhancing CPU performance through fabrication technologies and changes in chip designs but not as much luck has been struck with regards to the computer storage resulting in material negative system performance. A lot of research effort has been put on finding techniques that can improve the energy efficiency of cache architectures. This work is a survey of energy saving techniques which are grouped on whether they save the dynamic energy, leakage energy or both. Needless to mention, the aim of this work is to compile a quick reference guide of energy saving techniques from 2013 to 2016 for engineers, researchers and students.

show abstract

Design of Hybrid Second-Level Caches

Cited by 14 publications

References 37 publications

Notice of Violation of IEEE Publication Principles: A heterogeneous memory organization with minimum energy consumption in 3D chip-multiprocessors

Notice of Violation of IEEE Publication Principles: A heterogeneous memory organization with minimum energy consumption in 3D chip-multiprocessors

Read-Tuned STT-RAM and eDRAM Cache Hierarchies for Throughput and Energy Optimization

A Survey of Emerging Architectural Techniques for Improving Cache Energy Consumption

Contact Info

Product

Resources

About