Design of Improved Performance Voltage Controlled Ring Oscillator

Kinger, Bhawika; Suman, Shruti; Sharma, Kuldeep; Ghosh, P. K.

doi:10.1109/acct.2015.127

Cited by 20 publications

(2 citation statements)

References 4 publications

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“…In addition to that, power consumption of each design has been calculated using transient and DC analysis for dynamic and static power dissipation. Power consumption slightly increases for the bulk driver circuit due to external driver voltage and variation in threshold voltage of the transistor [18]. Tuning range, linearity, power dissipation and phase noise of the various methodologies without and with bulk bias are listed in Table 1.…”

Section: Comparative Resultsmentioning

confidence: 99%

Design and Analysis of Bulk-Driven Linear Voltage-Controlled Oscillator

Praharsha

Ommi

Raj

et al. 2021

Lecture Notes in Electrical Engineering

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Section: Comparative Resultsmentioning

confidence: 99%

Design and Analysis of Bulk-Driven Linear Voltage-Controlled Oscillator

Praharsha

Ommi

Raj

et al. 2021

Lecture Notes in Electrical Engineering

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“…Compared to the other works, the proposed approach occupies the least amount of space. A RO-VCO based on single-ended stages was presented in the cumulative work [24,25]. Its frequency ranges from 2.26 to 3.50 GHz, and its schematic simulations show a very low power consumption.…”

Section: State-of-the-art Comparisonmentioning

confidence: 99%

Asymmetric 5.5 GHz Three-Stage Voltage-Controlled Ring-Oscillator in 65 nm CMOS Technology

et al. 2023

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The current trend of increasing the complexity of hardware accelerators to improve their functionality is highlighting the problem of sharing a high-frequency clock signal for all integrated modules. As the clock itself is becoming the main limitation to the performance of accelerators, in this manuscript, we present the design of an asymmetric Ring Oscillator-Voltage-Controlled Oscillator (RO-VCO) based on the Current Mode Logic architecture. The RO-VCO was designed on commercial-grade 65 nm CMOS technology, and it is capable of driving large capacitance loads, avoiding the need for additional buffers for clock-trees, reducing the silicon area and power consumption. The proposed RO-VCO is composed of three closed-loop differential and asymmetrical stages, and it is able to tune the working frequency in the range from 4.72 GHz to 6.12 GHz. The phase noise and a figure of merit of −103.2 dBc/Hz and −186 dBc/Hz were obtained at 1 MHz offset from the 5.5 GHz carrier. In this article, the analytical model, full custom schematic, and layout of the proposed RO-VCO are presented and discussed in detail together with the experimental electrical and thermal characterization of the fabricated device.

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