Design of low logical cost adders using novel Parity Conserving Toffoli Gate

Saligram, Rakshith; Rakshith, T. R.

doi:10.1109/c2spca.2013.6749357

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2013

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Cited by 5 publications

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“…In reference [1] 4 bit reversible comparator based on reversible logic gates is designed to develop a system with low power consumption. In reference [2] PCTG (Parity Conserving Toffoli Gate) is introduced to overcome the issue of fault tolerant. The design has the most optimized performance parameters than its counterpart technology Reversible logic circuits are there to overcome this issue.…”

Section: Introductionmentioning

confidence: 99%

Design and Simulation of BIST based 4-Bit Binary Comparator based on Reversible Logic Architecture

Shrivastava¹,

Soni²

2016

IJCA

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In the present time, improvement of some fields like nanotechnology, low power design and quantum computing reversible logic circuit has emerged as a great prospect of research. With the help of using existing reversible gates a 4 bit reversible comparator based on classical logic circuit is represented. This work presents a BIST based architecture of a comparator design has a reduced number of constant inputs, garbage outputs and quantum cost.

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Section: Introductionmentioning

confidence: 99%