Design of low power and high speed modified carry select adder for 16 bit Vedic Multiplier

MAC based FIR filter: A novel approach for low-power real-time de-noising of ECG signals

“…Vedic Multiplier can also be used which uses the Urdhva-triyagbhyam Sutra [8] which is a simplistic algorithm but requires more hardware thus, more area. Using Radix-4 modified Booth's multiplier, the number of partial products are reduced to 'n/2' if we are multiplying two 'n' bits numbers, if 'n' is even number, or '(n+1)/2', if 'n' is an odd number.…”

Design of a Low Power and High Speed FIR filter based on Reusable MAC Unit

“…Vedic multiplier is faster than the array multiplier and Booth multiplier. The area needed for Vedic Multiplier is very small when compared to other multiplier architecture and the higher order multipliers can also be designed easily from lower order multipliers [4]. Carry Select Adder (CSA) is mainly used due to its low power consumption in the MAC unit and it also occupies less area.…”

HSTL IO Standard Based Energy Efficient Multiplier Design using Nikhilam Navatashcaramam Dashatah on 28nm FPGA

“…Implementation of 4*4 multiplier using Urdhva-Tiryakbhyam in 45nm technology [13], another division architecture using different Vedic technique known as `Dhwajam' [14]. Vedic multiplier has been designed earlier using different Vedic formulas but this design using Nikhilam Navatashcaramam Dashatah vedic formula is completely a fresh work and is quite efficient [20][21].In this paper we have designed an energy efficient multiplier that consists of three inputs and one output. The inputs are x, y and clock.…”