Design of Low Power Multiplier using CNTFET

Somineni, Rajendra Prasad; Jaweed, Shaik Mohammed

doi:10.1109/iacc.2017.0120

Cited by 7 publications

(3 citation statements)

References 3 publications

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“…The heart of the data security systems is RSA and ECC (Elliptical Curve Cryptography). However, nowadays NTRU is the most widely used algorithms in various cryptosystem play a major role in network security [11] [12].Montgomery put forth an algorithm that performs the modular multiplication without conducting any trial division but still generates some residue. An exponentiation operation that intensively performs modular multiplication is referred to as modular exponentiation.…”

Section: Montgomery Multipliermentioning

confidence: 99%

Performance Analysis of Montgomery Multiplier using 32nm CNTFET Technology

Mathan

Jayashri²,

Alias

et al. 2019

IJEEI

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VLSI design vacillating the parameters results in variation of critical factors like area, power and delay. The dominant sources of power dissipation in digital systems are the digital multipliers. A digital multiplier plays a major role in a mixture of arithmetic operations in digital signal processing applications hinge on add and shift algorithms. In order to accomplish high execution speed, parallel array multipliers are comprehensively put into application. The crucial drawback of these multipliers is that it exhausts more power than any other multiplier architectures. Montgomery Multiplication is the popularly used algorithm as it is the most efficient technique to perform arithmetic based calculations. A high-speed multiplier is greatly coveted for its extraordinary leverage. The primary blocks of a multiplier are basically comprised of adders. Thus, in order to attain a significant reduction in power consumption at the chip level the power utilization in adders can be decreased. To obtain desired results in performance parameters of the multiplier an efficient and dynamic adder is proposed and incorporated in the Montgomery multiplier. The Carbon Nanotube field effect transistor (CNTFET) is a promising new device that may supersede some of the fundamental limitations of a silicon based MOSFET. The architecture has been designed in 130nm and 32nm CMOS and CNTFET technology in Synopsys HSpice. The analysed parameters that are considered in determining the performance are power delay product, power and delay and comparison is made with both the technologies.The simulation results of this paper affirmed the CNTFET based Montgomery multiplier improved powerconsumption by 76.47%,speed by 72.67% and overall energy by 67.76% as compared to MOSFET-based Montgomery multiplier.

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Section: Montgomery Multipliermentioning

confidence: 99%

Performance Analysis of Montgomery Multiplier using 32nm CNTFET Technology

Mathan

Jayashri²,

Alias

et al. 2019

IJEEI

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“…Hence, we need to find a way to reduce the power dissipation and increase the efficiency of the system so that the processor can meet the needs of power utilization. Multiplier performance is directly linked to the performance of the adders used in it [3]. So, we can decrease the power dissipation and increase the efficiency of processor by concentrating on the internal adders and circuit of multiplier.…”

Section: Introductionmentioning

confidence: 99%

Design of Wallace tree multiplier circuit using high performance and low power full adder

Leela,

Manisha,

Bharath

et al. 2023

E3S Web Conf.

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The act of multiplying includes adding partial products repeatedly, and conventional multipliers call for many adders to perform partial product addition in higher order multiplication. A multiplier’s effectiveness and efficiency are evaluated using parameters such as speed, time delay, area, Power Delay Product (PDP), accuracy, and power consumption. In order to choose the optimum multiplier, this project is to evaluate various multipliers their performance metrics. Then, suggests employing a hybrid technology-based adder to improve the performance of the selected multiplier. The power consumption of the multiplier can be significantly reduced while maintaining the required accuracy by using a hybrid technology-based adder and low power full adders. This will allow multipliers to be used in low-power applications where power consumption is a major concern. To summarize, the goal of this project is to design and compare different multipliers using H-spice coding, as well as to improve the performance of the chosen. This project used 4x4 multiplier evaluation using 32nm technology.

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“…The TGM FAC [4] is designed by using the 25 transistors, MNM FAC [5] is designed by using the 26 transistors, proposed TGMM FAC is designed only by using the 23 transistors and another proposed MNMM FAC is designed only by using the 18 transistors. This paper is structured as follows Section-2 presents the Review of CMOS, CNTFET and GNRFET.…”

Section: Introductionmentioning

confidence: 99%

Design and analysis of different full adder cells using new technologies

Kumar

Somineni

Kumari

2020

IJRES

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<span>CMOS transistors are most widely used for the design of computerized circuits, when scaling down the nanometer technology these devices faces the short channel effects and causes I-V characteristics to depart from the traditional MOSFETs, So the researchers have developed the other transistors technologies like CNTFET and GNRFET. Carbon nanotube field effect transistor is one of the optimistic technologies and it is a three terminal transistor similar to MOSFET. The semiconducting channel between the two terminals called source and drain comprises of the nano tube which is made of carbon. Graphene nano ribbon filed effect transistor is the most optimistic technology here the semiconducting channel is made of graphene. When contrasted with barrel shaped CNTFETs, GNRFETs can be prepared in situ process, transfer-free and silicon compatible, thus have no passage related and alignment problems as faced in CNTFET devices. This paper presents different 1-bit Full Adder Cells (FACs) like TG MUX-based FAC (TGM), MN MUX-based FAC (MNM), proposed TG Modified MUX-based FAC (TGMM) and another proposed MN Modified MUX-based FAC (MNMM) are designed using different technologies like CNTFET and GNRFET at 16nm technology with supply voltage of 0.85v and simulation is done by using Synopsys HSPICE Tool and the proposed designs are best when compared to the TGM and MNM FACs in terms of Static and Dynamic powers Dissipations and Delay.</span>

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Design of Low Power Multiplier using CNTFET

Cited by 7 publications

References 3 publications

Performance Analysis of Montgomery Multiplier using 32nm CNTFET Technology

Performance Analysis of Montgomery Multiplier using 32nm CNTFET Technology

Design of Wallace tree multiplier circuit using high performance and low power full adder

Design and analysis of different full adder cells using new technologies

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