Design of nano scale CMOS full adder with low leakage and ground bounce noise reduction

Goyal, Candy; Ubhi, Jagpal Singh; Raj, Balwinder

doi:10.1109/icspcom.2016.7980610

Cited by 3 publications

(3 citation statements)

References 13 publications

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“…Circuit structures with different applied clocks can also help in achieving power and speed efficiency [32][33]. Transistor gating techniques can also be used for power reduction but it suffers from poor reliability due to ground bounce problem which can further be overcome by sleep transistor [34]. FinFETs can be the replacement of MOSFETs when power efficiency is required at nano meter technologies.…”

Section: Previous Contributionmentioning

confidence: 99%

Sleepy- Gate Diffusion Input (S-GDI) — Ultra Low Power Technique for Digital Design

Sharma*,

Sohal

2019

IJITEE

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In this paper we propose a power efficient technique called Sleepy- Gate Diffusion Input (S-GDI) that can be used for efficient digital design at nano scale foundries. For area and power comparison, ten prior techniques are taken in to consideration and applied on XOR gate, 1-bit adder, 1-bit comparator and 4- bit up-down counter. All techniques are parametrically analyzed on 65nm technology. The proposed S-GDI technique has been observed power efficient as compared to Complementary CMOS technique (CCT), Complementary Pass Transistor Logic (CPTL), DCMOS (Differential CMOS), Differential Cascode Voltage Switch with Pass Gate Logic (DCVSPG), Energy Economized Pass Transistor Logic (EEPL), Lean Integration with Pass Transistors (LEAP), Push-Pull Pass Transistor Logic (PPL), Pass Transistor Logic (PTL), CMOS with Transmission Gate (TG) and Gate diffusion Input (GDI). As compared to GDI technique S-GDI is showing 96.20%, 93.65%, 97.88% and 98.22% power efficiency for XOR, 1-bit adder, 1-bit comparator and 4-bit up-down counter respectively. S-GDI is showing area efficiency of 17.16% and 28.1% for XOR, 41.26% and 53.89% for 1-bit adder, 7.6% and 21.76% for 1-bit comparator and 6.7% and 28% for up-down counter over EEPL and DCMOS technique respectively. Although other techniques except EEPL and DCMOS techniques are area efficient as compared to proposed technique but this is on the expense of higher total power dissipation. So, PDP (power delay products) of all considered techniques are also calculated on 65nm technology for both SUM and CARRY outputs of 1-bit adder. In both cases power delay product for S-GDI technique is very less as compared to all other considered technique. Due to efficiency of S-GDI in terms of considered parameters, this technique can be efficiently used for low power applications

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Section: Previous Contributionmentioning

confidence: 99%

Sleepy- Gate Diffusion Input (S-GDI) — Ultra Low Power Technique for Digital Design

Sharma*,

Sohal

2019

IJITEE

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“…If there is a movement, then corresponding shadows will exist in the resultant picture. We have used two's complement for subtraction of n 2 (i,j) matrices which is shown in (9).…”

Section: Motion Detection Using Proposed Approximate Fasmentioning

confidence: 99%

“…However, a very few circuits are optimized for leakage power. Recently a sleep circuit with three NMOS transistors and one PMOS transistor is presented [9], which reduces leakage power and GBN but requires large silicon area. A circuit with tri-mode [10] is used to reduce leakage current and GBN which has a park mode between active and standby mode.…”

Section: Introductionmentioning

confidence: 99%

A Reliable Leakage Reduction Technique for Approximate Full Adder with Reduced Ground Bounce Noise

Goyal¹,

Ubhi

Raj

2018

Mathematical Problems in Engineering

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In this paper, an effective and reliable sleep circuit is proposed, which not only reduces leakage power but also shows significant reduction in ground bounce noise (GBN) in approximate full adder (FA) circuits. Four 1-bit approximate FA circuits are modified using proposed sleep circuit which uses one NMOS and one PMOS transistor. The design metrics such as average power, delay, power delay product (PDP), leakage power, and GBN are compared with nine other 1-bit FA circuits reported till date. All the comparisons are done using post-layout netlist at 45nm technology. The modified designs achieve reduction in leakage power and GBN up to 60% and 80%, respectively, as compared to the best reported approximate FA circuits. The modified approximate FA also achieves 83% reduction in leakage power as compared to conventional FA. Finally, application level metrics such as peak signal to noise ratio (PSNR) are considered to measure the performance of all the proposed approximate FAs.

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Sleepy CMOS-Sleepy Stack (SC-SS): A Novel High Speed, Area and Power Efficient Technique for VLSI Circuit Design

Sharma

Sohal

Kaur

2019

J CIRCUIT SYST COMP

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This paper presents a novel ultra-low-power Sleepy CMOS-Sleepy Stack (SC-SS) technique for nano scale VLSI technologies. Eight prior techniques are taken for comparison with proposed technique on 65[Formula: see text]nm technology. All the techniques are applied on four benchmark circuits: XOR gate, 1-bit adder, 1-bit comparator and 4-bit up-down counter for measurement of area consumption and total power dissipation. The proposed SC-SS technique achieved very high power efficiency as compared to Complementary CMOS technique (CCT), Dual sleep Technique (DST), Forced stack technique (FST), Sleepy keeper technique (SKT), Sleepy pass gate technique (SPGT), Sleep transistor technique (STT) and VLSI CMOS Circuit Leakage Reduction technique (VCLEARIT). Although Sleepy stack technique (SST) is power efficient as compared to SC-SS technique, this is on the expense of area and delay penalty. Proposed technique has shown the area improvement of 33% for XOR, 10.78 % for 1-bit adder, 14.9% for 1-bit comparator and 9.7% for 4-bit up-down counter over SST technique on 65[Formula: see text]nm technology. At the same time, power-area product of SC-SS is 29.56% and 54.96% less as compared to SST for XOR and 4-bit up-down counter. To obtain the efficiency of proposed technique over SST in terms of delay and power-delay product, basic inverter design is taken into consideration. Delay of SC-SS inverter is 34.8% and power-delay product is 6.9% less as compared to SST inverter on 65[Formula: see text]nm technology.

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Design of nano scale CMOS full adder with low leakage and ground bounce noise reduction

Cited by 3 publications

References 13 publications

Sleepy- Gate Diffusion Input (S-GDI) — Ultra Low Power Technique for Digital Design

Sleepy- Gate Diffusion Input (S-GDI) — Ultra Low Power Technique for Digital Design

A Reliable Leakage Reduction Technique for Approximate Full Adder with Reduced Ground Bounce Noise

Sleepy CMOS-Sleepy Stack (SC-SS): A Novel High Speed, Area and Power Efficient Technique for VLSI Circuit Design

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