Design of On-Wafer TRL Calibration Kit for InP Technologies Characterization up to 500 GHz

Abstract

This paper reports a detailed approach towards optimization of on-wafer TRL calibration structures for submillimeter-wave characterization of a state-of-the-art InP technology, validated by thorough experimentation and electromagnetic (EM) simulation. The limitations of the existing RF test structures for high frequency measurements beyond 110 GHz are analyzed through EM simulation. Using an optimization procedure based on calibration of raw EM simulated data, onwafer TRL calibration structures were developed and fabricated in a subsequent run of this technology. Measurements could be achieved up to 500 GHz on the passive devices and up to 330 GHz on the InP DHBTs. The transistor measurements were validated by comparison with the HiCuM compact model simulation to 330 GHz for the InP DHBTs.

InP/GaAsSb Double Heterojunction Bipolar Transistor Emitter-Fin Technology With f MAX = 1.2 THz

“…Work is under way to implement the present emitter fin device architecture using improved probe pad designs and onwafer calibration structures along the lines of [14] to enable meaningful device characterization well above 100 GHz.…”

“…Extrapolations at -20 dB/dec of the modeled U model from 50 GHz ≤ f ≤ 0.5 THz confirm the experimentally determined f MAX = 1.2 THz. Work is under way to characterize the emitter fin DHBTs at higher frequencies using E&M optimized probing and on-wafer calibration structures (not included in the present process development mask set) [14]. Past experience shows extension to higher measurement frequencies does not affect conclusions drawn from measurements up to 50 GHz on our transistors [14].…”

Towards Monolithic Indium Phosphide (InP)-Based Electronic Photonic Technologies for beyond 5G Communication Systems

“…In [25], coplanar waveguide (CPW) transmission lines in InP technology proved to be suitable for on-wafer TRL calibration for InP DHBT characterization up to 500 GHz. Hence, the same methodology for designing calibration structures was applied to the III-V Lab InP DHBT process (Figure 12).…”

InP DHBT Characterization up to 500 GHz and Compact Model Validation Towards THz Circuit Design

“…The on-wafer calibration kit was designed so as to apply the Thru-Reflect-Line (TRL) method, well known to be efficient for accurate S-parameter measurements beyond 110 GHz on both This work was supported partly by the Agence Nationale de la Recherche in the frame of the project ULTIMATE (ANR-16-CE93-0007) and partly by the Région Nouvelle-Aquitaine authorities through the FAST project. 1µm silicon and InP heterojunction transistors characterization [9]- [13]. Well-known for its robustness and traceability, the TRL method, based on only three standards, is also easy to implement, since two transmission line, one Thru and one Line, need to be designed, as well as a symmetrical Reflect, either open or short-type.…”

“…2, the TRL calibration standards were located in the periphery of the chip. A continuous ground plane was implemented as recommended in [12] and [13] with the support of electromagnetic simulation so as to minimize the coupling between the RF probes and the substrate. Then, all the ground pads of each test structure are connected together through this continuous ground plane.…”