Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications

Abstract

To meet the requirements of both costeffectiveness and high reliability for low-orbit aerospace applications, this paper first presents a radiation hardened latch design, namely HLCRT. The latch mainly consists of a single-node-upset self-recoverable cell, a 3input C-element, and an inverter. If any two inputs of the C-element suffer from a double-node-upset (DNU), or if one node inside the cell together with another node outside the cell suffer from a DNU, the latch still has a correct value on its output node, i.e., the latch is effectively DNU hardened. Based on the latch, this paper also presents a flip-flop, namely HLCRT-FF that can tolerate SNUs and DNUs. Simulation results demonstrate the SNU/DNU tolerance capability of the proposed HLCRT latch and HLCRT-FF. Moreover, due to the use of a few transistors, clock gating technologies, and high-speed paths, the proposed HLCRT latch and HLCRT-FF approximately save 61% and 92% of delay, 45% and 55% of power, 28% and 28% of area, and 84% and 97% of delay-power-area product on average, compared to state-of-the-art DNU hardened latch/flip-flop designs, respectively.

Low cost and high performance double‐node upset resilient latch for low orbit space applications

“…Changes in process, voltage, and temperature (PVT) can significantly impact on the design performance of the storage elements, particularly latches. 18,22,28,29 In Figure 7, the PVT variation assessment results for delay and power of the latches are shown. The nominal supply voltage has been kept at 1 V, ranging from 0.8 to 1.2 V. The normal temperature is kept at 25 C and ranges from À25 C to 125 C. Threshold voltage (V th ) values are deviated ±0.1 V from their original values.…”

“…Moreover, SEs induced by DNUs are becoming more significant, and the rate of such errors in circuits and systems is increasing due to DNUs 16 . Low orbit space applications and even terrestrial medical equipment, subject to modest radiation impacts, often experience SNUs and DNUs as the most common errors 17,18 . DNU hardening is therefore necessary for robust computing in low orbit space applications.…”

“…16 Low orbit space applications and even terrestrial medical equipment, subject to modest radiation impacts, often experience SNUs and DNUs as the most common errors. 17,18 DNU hardening is therefore necessary for robust computing in low orbit space applications.…”

Wrap-Gate CNT-MOSFET Based SRAM Bit-Cell with Asymmetrical Ground Gating and Built-In Read-Assist Schemes for Application in Limited-Energy Environments

“…5,6 Since SNUs and/or DNUs in the worst case can lead to systemlevel soft errors, so they can be eliminated by data reloading or online self-recovering using the popular radiation-hardening-bydesign (RHBD) approach (as low-cost circuit-level design solution) and/or layout-based solutions (such as isolation, node spacing increase and guard rings). 7,8 Since a conventional SRAM cell structure, namely 6-transistors (6 T), cannot tolerate various kinds of node upsets, 9,10 so far, several designs of SRAM cells have been proposed by designers of integrated circuit (IC) chips through the RHBD approach to mitigate SNUs and MNUs. So far, various differential (dual) and single bitline radiation hardened SRAM cells have been published by researchers which can tolerate SNUs and MNUs, in typical types (based on basic structure in radiation hardened memory cells such as dual interlocked storage cell (DICE), 11 Quatro, 12 ), terrestrial (low-orbit) and aerospace (highorbit) applications using RHDB and layout approaches.…”

“…So far, various differential (dual) and single bitline radiation hardened SRAM cells have been published by researchers which can tolerate SNUs and MNUs, in typical types (based on basic structure in radiation hardened memory cells such as dual interlocked storage cell (DICE), 11 Quatro, 12 ), terrestrial (low-orbit) and aerospace (highorbit) applications using RHDB and layout approaches. [13][14][15][16][17][18][19][20][21][22][23][24][25] In the literature, 19,20 some asymmetrical hardened SRAM cells, where some symmetrical bitline hardened SRAM cells in literatures, [6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21] are proposed. Also, single bitline (or single-ended) hardened SRAM cells based on Muller C-elements are proposed in referances.…”