Design of switching blocks tolerating defects/faults in FPGA interconnection resources

Doumar, Abderrahim; Ito, Hideo

doi:10.1109/dftvs.2000.887151

Cited by 9 publications

(6 citation statements)

References 15 publications

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“…Saha et al [29] suggests introducing error correcting codes to the LUTs in the Cell Matrix architecture. Doumar and Ito [11] add an extra wire to the switch block to provide a bypass for a faulty switch.…”

Section: Defect Tolerance For Fpgasmentioning

confidence: 99%

The route to a defect tolerant LUT through artificial evolution

Djupdal¹,

Haddow²

2011

Genet Program Evolvable Mach

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Evolutionary techniques may be applied to search for specific structures or functions, as specified in the fitness function. This paper addresses the challenge of finding an appropriate fitness function when searching for generic rather than specific structures which, when combined wiacteristic of defect tolerance on the circuit. Production defects for integrated circuits are expected to increase considerably. To avoid a corresponding drop in yield, improved defect tolerance solutions are needed. In the case of Field Programmable Gate Arrays (FPGAs), the predesigned gate array provides a bridge between production and the application designers. Thus, introduction of defect tolerant techniques to the FPGA itself could provide a defect free gate array to the application designer, despite production defects. The search for defect tolerance presented herein is directed at finding defect tolerant structures for an important building block of FPGAs: Look-Up Tables (LUTs). Two key approaches are presented: (1) applying evolved generic building blocks to a traditional LUT design and (2) evolving the LUT design directly. The results highlight the fact that evolved generic defect tolerant structures can contribute to highly reliable circuit designs at the expense of area usage. Further, they show that applying such a technique, rather than direct evolution, has benefits with respect to evolvability of larger circuits, again at the expense of area usage.

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Section: Defect Tolerance For Fpgasmentioning

confidence: 99%

The route to a defect tolerant LUT through artificial evolution

Djupdal¹,

Haddow²

2011

Genet Program Evolvable Mach

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“…An alternative to the coarse-grained approach of adding complete rows or columns of logic is a more fine-grained approach of adding additional switches throughout the FPGA interconnect [73,240]. With another set of switches, connections can be shifted to avoid defective routing segments.…”

Section: Manufacturing Defectsmentioning

confidence: 99%

FPGA Architecture: Survey and Challenges

Kuon

Tessier

Rose

2008

FNT in Electronic Design Automation

331

109

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Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. FPGA architecture has a dramatic effect on the quality of the final device's speed performance, area efficiency, and power consumption. This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures. We include a survey of the key elements of modern commercial FPGA architecture, and look toward future trends in the field.

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“…For example, additional connections can be added inside the switch block to tolerate one transistor defect per switch block [8]. Unfortunately, this approach is impractical because it significantly alters delay.…”

Section: Hardware-based Redundancymentioning

confidence: 99%

Defect-tolerant fpga switch block and connection block with fine-grain redundancy for yield enhancement

Lemieux

International Conference on Field Programmable Logic and Applications, 2005.

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Future process nodes have such small feature sizes that there will be an increase in the number of manufacturing defects per die. For large FPGAs, it will be critical to tolerate multiple defects [6]. We propose a number of changes to the detailed routing architecture of island-style FPGAs to tolerate multiple random, distributed interconnect defects without re-routing and with minimal impact on signal timing. Our scheme is a user option prebuilt into an architecture, requiring +11% area for additional multiplexers. Unused (spare) wiring tracks are also needed, bringing total overhead to 24% to tolerate stuck-at or open faults, or 34% to include bridging. User circuits that do not fully stress the routing network already have these tracks freely available. The delay penalty is programmable: 5-10% if defect rates are expected to be sufficiently low, but can be as high as 25% if defect rates are high. Our schemes can tolerate more than 10 interconnect defects for large array sizes of 128 × 128. Unlike row/column redundancy schemes, our schemes are scalable: they naturally tolerate more defects as the FPGA array size increases. This work is the first detailed analysis of fine-grained defect-tolerant schemes in FPGAs.

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Design of switching blocks tolerating defects/faults in FPGA interconnection resources

Cited by 9 publications

References 15 publications

The route to a defect tolerant LUT through artificial evolution

The route to a defect tolerant LUT through artificial evolution

FPGA Architecture: Survey and Challenges

Defect-tolerant fpga switch block and connection block with fine-grain redundancy for yield enhancement

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