Design of Ultra-Low Power Consumption Approximate 4–2 Compressors Based on the Compensation Characteristic

Pei, Haoran; Yi, Xilin; Zhou, Hang; He, Yajuan

doi:10.1109/tcsii.2020.3004929

Cited by 49 publications

(12 citation statements)

References 11 publications

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“…In Ref. [7], the researchers proposed three novel approximate 4-2 compressors, where the number of outputs of the approximate 4-2 compressor is reduced to one and utilized in an 8-bit multiplier. Additionally, an error correction module (ECM) is proposed to facilitate the error performance of the approximate multipliers with the proposed 4-2 compressors.…”

Section: Related Workmentioning

confidence: 99%

A Piecewise Linear Mitchell Algorithm-Based Approximate Multiplier

et al. 2022

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In the field of integrated circuits, the computational cost has always been a crucial design metric. In recent years, with the continuous development in the field of computing, the requirements for computation have been growing rapidly. Reducing the computational cost and improving computational efficiency have become the key issues in the field. There are many error-tolerant applications in the multimedia field where approximate computing techniques can be applied to improve computational efficiency and reduce computational costs at the cost of acceptable computational errors. This paper proposed a piecewise linear Mitchell algorithm based on Mitchell logarithmic approximation multiplication algorithm. Additionally, the Pwl-Mit multiplier is designed according to the improved algorithm combined with the data truncation technique. The proposed approximate multiplier has better statistical performance compared with the state-of-the-art multipliers. The design is simulated and synthesized at the TSMC 65 nm process, and its reliability is verified using discrete cosine transform (DCT) transform.

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Section: Related Workmentioning

confidence: 99%

A Piecewise Linear Mitchell Algorithm-Based Approximate Multiplier

et al. 2022

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“…Pei et al [20] developed three new, approximate 4-2 multiplier compressors for 8-Bit utilization. In addition, an error correction module (ECM) is suggested for improved error performance of the approximate multiplier during implementing the 4-2 compressors.…”

Section: Literature Surveymentioning

confidence: 99%

“…To get the product of the inputs, accumulate the reduced set of partial products after Wallace tree reduction [14]. We use new inexact half adders and full adders to add partial products by changing the design so that better it would achieve outcomes concerning delay [2,20]. Here in this study, we suggest few designs for inexact adders with reduced gate counts.…”

Section: Final Partial Product Additionmentioning

confidence: 99%

Design of high speed approximate multipliers with inexact compressor adder

Sudharani¹,

Sreenivasulu²

2021

IJATEE

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In most practical applications, accurate results are unnecessary, hence approximate computation is being used. By using approximate computing the system performance metrics like area, power and speed can be improved. This paper proposes an approximate circuit that was developed by modifying the circuit architecture but not the circuit operation. We propose an approximate multiplier using these approximate circuits, which use AND-OR logic approximation, Wallace tree reduction, and 3:2 inexact additive designs for partial product generation and addition. In this paper, by taking an 8X8 bit multiplication as an example, we show the whole proposed concept. Also, the proposed multipliers will cause substantial improvements in terms of both area and delay. Compared to the conventional multipliers, the AWM1 achieves up to 35.577% reduction in area and 35.224% in delay. AWM2 has an area and delay reductions of up to 48.077% and 36.532% respectively. AWM3 has area savings of up to 48.077% and delay reductions of up to 46.633%. Finally, the AWM4 has area savings of up to 53.846% and delay reductions of up to 56.482%.

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“…Approximate 4:2 designs implemented in FinFET technology are presented in [33], [35]. In [34] the number of outputs of the approximate 4:2 compressor is innovatively reduced to one; 3 such compressors are proposed, as well as an errorcorrecting module.…”

Section: Introductionmentioning

confidence: 99%

Approximate Recursive Multipliers Using Low Power Building Blocks

Zacharelos

Nunziata

Saggese

et al. 2022

IEEE Trans. Emerg. Topics Comput.

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Approximate computing, frequently used in error tolerant applications, aims to achieve higher circuit performances by allowing the possibility of inaccurate results, rather than guaranteeing a correct outcome. Many contributions target the binary multiplier aiming to minimize the complexity of this common yet power-hungry circuit. Approximate recursive multipliers are low-power designs that exploit approximate building blocks to scale up to their final size. In this paper, we present two novel 4x4 approximate multipliers obtained by carry manipulation. They are used to compose 8x8 designs with different error-precision trade-off. The final circuits exhibit a competitive behavior in terms of error while reducing the power dissipation when compared to state-of-the-art proposals. The proposed multipliers and state-of-the-art designs found in the literature, have been synthesized targeting a 14nm FinFET technology to determine the electrical characteristics. Compared with an exact 8×8 multiplier, the least dissipative design proposed in this paper reduces power consumption and silicon area by 46%, and minimum delay by 21%. It also consumes 14% less power than the least power-hungry recursive circuit found in the literature, while offering 81% higher accuracy. Ιmage processing applications and a convolutional neural network are shown to demonstrate the effectiveness of the proposed multipliers.

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Design of Ultra-Low Power Consumption Approximate 4–2 Compressors Based on the Compensation Characteristic

Cited by 49 publications

References 11 publications

A Piecewise Linear Mitchell Algorithm-Based Approximate Multiplier

A Piecewise Linear Mitchell Algorithm-Based Approximate Multiplier

Design of high speed approximate multipliers with inexact compressor adder

Approximate Recursive Multipliers Using Low Power Building Blocks

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