Design of Vedic IEEE 754 floating point multiplier

Havaldar, Soumya; Gurumurthy, K. S.

doi:10.1109/rteict.2016.7808008

Cited by 12 publications

(6 citation statements)

References 1 publication

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“…The plan uses lesser giant kind of LUT's, consequently diminishes the electricity usage. Soumya Havaldar, adequate S Gurumurthy [4] proposed the structure of multiplier for drifting thing numbers using vedic generation. This shape likewise oversees flood, sub-modern-day-day and adjusting.…”

Section: Preceding Paintingsmentioning

confidence: 99%

Research on IEEE 754 Standard Single Precision Floating Point Multipliers Designed using Urdhva Triyagbhyam Sutra of Vedic Mathematics

Prasada

Seshikala

Niranjana

2019

IJRTE

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Duplication of the coasting element numbers is the big activity in automated signal handling. So the exhibition of drifting problem multipliers count on a primary undertaking in any computerized plan. Coasting factor numbers are spoken to utilizing IEEE 754 modern day in single precision(32-bits), Double precision(sixty four-bits) and Quadruple precision(128-bits) organizations. Augmentation of those coasting component numbers can be completed via using Vedic generation. Vedic arithmetic encompass sixteen wonderful calculations or Sutras. Urdhva Triyagbhyam Sutra is most usually applied for growth of twofold numbers. This paper indicates the compare of tough work finished via exceptional specialists in the direction of the plan of IEEE 754 ultra-modern-day unmarried accuracy skimming thing multiplier the usage of Vedic technological statistics.

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Section: Preceding Paintingsmentioning

confidence: 99%

Research on IEEE 754 Standard Single Precision Floating Point Multipliers Designed using Urdhva Triyagbhyam Sutra of Vedic Mathematics

Prasada

Seshikala

Niranjana

2019

IJRTE

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“…Implementation was done using Vedic Mathematics using same approach outlined in [17]. The system of [27] computed the biased exponent by the summation of both biased exponents of inputs using binary adders followed by subtraction of the bias. The mantissa multiplication component of the single precision multiplier was implemented using a 24x24 Vedic Multiplier while the double precision mantissa multiplication was done using a 53x53 Vedic Multiplier as shown in Figure VI.…”

Section: Double Precision Floating-point Multiplicationmentioning

confidence: 99%

“…Table VIII presents the area utilization for the double precision floating-point multiplier of [27] while Table IX presents the delay comparison for previous system from [17] and proposed system from [27]. [27] [4] presented a pipelined IEEE floating-point multiplier system which was capable of carrying out either single-precision or double precision multiplication. [4] claims that the latency of the system in single precision operation was 2 cycles while in double-precision operation it was 3 cycles.…”

Section: Double Precision Floating-point Multiplicationmentioning

confidence: 99%

“…At the same time there is no implementation of the binary multiplier that can be utilized for all four floating-point multiplier modessingle, double, quadruple and octuple precisions modes. Only a few such as the multiplier of [27] and others catered for multi-precision and at best processed 2 batches of input single precision floating-point numbers or 1 in double precision mode. The development of such a system is also a viable consideration.…”

Section: Considerations For Development Of Novel Floating-point Multimentioning

confidence: 99%

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Comparative Review of Floating-Point Multiplier Systems

George¹,

Tobago²

2019

IJHIT

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This paper presents a comprehensive comparative review of existing floating-point multiplier systems. The study focuses on single, double, quadruple and multi-precision floating point multiplier architectures and seeks to identify engineering techniques involved in their development. A comparison of the performance of these systems in terms of metrics such as path delay, hardware utilization and even power consumption in some case are carried out. Weaknesses in the systems reviewed along with possible gaps in the area of research are identified. This paper also serves to identify several recommendations and considerations for the development of a multi-precision floating point multiplier system capable of treating with the weaknesses of multiplier systems identified.

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“…This delay is significantly less than Booth multiplier. Soumya Havaldar, K S Gurumurthy [4] proposed the design of multiplier for floating point numbers using vedic mathematics. This design also manages overflow, underflow and rounding.…”

Section: Previous Workmentioning

confidence: 99%

Design of High Speed 32-bit Floating Point Multiplier using Urdhva Triyagbhyam Sutra of Vedic Mathematics

Prasada¹,

Seshikala²,

Niranjana

2019

ijrte

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Multiplication of floating point(FP) numbers is greatly significant in many DSP applications. The performance of the DSP’s is substantially decided by the speed of the multipliers used. This paper proposes the design and implementation of IEEE 754 standard single precision FP multiplier using Verilog, synthesized and simulated in Xilinx ISE10.1. Urdhva Triyagbhyam Sutra of Vedic mathematics is used for the unsigned mantissa calculation. The design implements floating point multiplication with sign bit and exponent calculations. The proposed design is achieved high speed with minimum delay of 3.997ns.Multiplication of floating point(FP) numbers is greatly significant in many DSP applications. The performance of the DSP’s is substantially decided by the speed of the multipliers used. This paper proposes the design and implementation of IEEE 754 standard single precision FP multiplier using Verilog, synthesized and simulated in Xilinx ISE10.1. Urdhva Triyagbhyam Sutra of Vedic mathematics is used for the unsigned mantissa calculation. The design implements floating point multiplication with sign bit and exponent calculations. The proposed design is achieved high speed with minimum delay of 3.997ns.

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Design of Vedic IEEE 754 floating point multiplier

Cited by 12 publications

References 1 publication

Research on IEEE 754 Standard Single Precision Floating Point Multipliers Designed using Urdhva Triyagbhyam Sutra of Vedic Mathematics

Research on IEEE 754 Standard Single Precision Floating Point Multipliers Designed using Urdhva Triyagbhyam Sutra of Vedic Mathematics

Comparative Review of Floating-Point Multiplier Systems

Design of High Speed 32-bit Floating Point Multiplier using Urdhva Triyagbhyam Sutra of Vedic Mathematics

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