Design Optimization of Silicon-based Junctionless Fin-type Field-Effect Transistors for Low Standby Power Technology

Abstract

-Recently, the junctionless (JL) transistors realized by a single-type doping process have attracted attention instead of the conventional metal-oxide-semiconductor field-effect transistors (MOSFET). The JL transistor can overcome MOSFET's problems such as the thermal budget and short-channel effect. Thus, the JL transistor is considered as great alternative device for a next generation low standby power silicon system. In this paper, the JL FinFET was simulated with a three dimensional (3D) technology computer-aided design (TCAD) simulator and optimized for DC characteristics according to device dimension and doping concentration. The design variables were the fin width (W fin ), fin height (H fin ), and doping concentration (D ch ). After the optimization of DC characteristics, RF characteristics of JL FinFET were also extracted.

Performance optimization of tri-gate junctionless FinFET using channel stack engineering for digital and analog/RF design

“…The presence of SiGe in the channel region of the stacked channel FinFET increases the electron mobility, resulting in higher output transconductance in the TLSC and DLSC structures. This is because the electrons experience less resistance to their motion, and are able to Junctionless accumulation mode FinFET [23] Junctionless FinFET [24] Junctionless bulk FinFET [25] Gate flow more freely through the channel region. The output transconductance is obtained at a fixed gate voltage.…”