Design Patterns for Reconfigurable Computing

DeHon, André; Adams, Jay K.; deLorimier, Michael; Kapre, Nachiket; Matsuda, Yuki; Naeimi, Helia; Vanier, Michael; Wrighton, Michael G.

doi:10.1109/fccm.2004.29

Cited by 45 publications

(27 citation statements)

References 95 publications

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“…Compile-time selection of strategy objects is an admissible form of the design pattern, and is suited to hardware implementation. Other authors have also recognized the value of design patterns in hardware design [22][23][24], so one may look forward to support for these high-level design constructs in the future.…”

Section: Component Hierarchymentioning

confidence: 99%

Families of FPGA-based accelerators for approximate string matching

Court

Herbordt

2007

Microprocessors and Microsystems

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Dynamic programming for approximate string matching is a large family of different algorithms, which vary significantly in purpose, complexity, and hardware utilization. Many implementations have reported impressive speed-ups, but have typically been point solutions -highly specialized and addressing only one or a few of the many possible options. The problem to be solved is creating a hardware description that implements a broad range of behavioral options without losing efficiency due to feature bloat. We report a set of three component types that address different parts of the approximate string matching problem. This allows each application to choose the feature set required, then make maximum use of the FPGA fabric according to that application's specific resource requirements. Multiple, interchangeable implementations are available for each component type. We show that these methods allow the efficient generation of a large, if not complete, family of accelerators for this application. This flexibility was obtained while retaining high performance: We have evaluated a sample against serial reference codes and found speed-ups of from 150× to 400× over a high-end PC.

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Section: Component Hierarchymentioning

confidence: 99%

Families of FPGA-based accelerators for approximate string matching

Court

Herbordt

2007

Microprocessors and Microsystems

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“…Streaming, systolic, and associative computing structures, and arrays of fine-grained automata, are preferable. 6 Application example-Finding information about a newly discovered gene or protein by searching biomedical databases for similar sequences is a fundamental bioinformatics task. The most commonly used applications are based on the basic local alignment search tool, which operates in multiple phases.…”

Section: Methods 2:use a Computing Mode Appropriate For Fpgasmentioning

confidence: 99%

Achieving High Performance with FPGA-Based Computing

et al. 2007

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Numerous application areas, including bioinformatics and computational biology, demand increasing amounts of processing capability. In many cases, the computation cores and data types are suited to field-programmable gate arrays. The challenge is identifying the design techniques that can extract high performance potential from the FPGA fabric.Accelerating high-performance computing (HPC) applications with field-programmable gate arrays (FPGAs) can potentially deliver enormous performance. A thousand-fold parallelism is possible, especially for low-precision computations. Moreover, since control is configured into the logic itself, overhead instructions-such as array indexing and loop computationsneed not be emulated, and every operation can deliver payload.At the same time, using FPGAs presents significant challenges 1 including low operating frequency-an FPGA clocks at one-tenth that of a high-end microprocessor. Another is simply Amdahl's law: To achieve the speedup factors required for user acceptance of a new technology (preferably 50 times), 2 at least 98 percent of the target application must lend itself to substantial acceleration. As a result, HPC/FPGA application performance is unusually sensitive to the implementation's quality.The problem of achieving significant speedups on a new architecture without expending exorbitant development effort, and while retaining flexibility, portability, and maintainability, is a classic one. In this case, accelerating HPC applications with FPGAs is similar to that of porting uniprocessor applications to massively parallel processors, with two key distinctions:• FPGAs are far more different from uniprocessors than MPPs are from uniprocessors, and• the process of parallelizing code for MPPs, while challenging, is still better understood and supported than porting codes to FPGAs.Lawrence Snyder stated the three basic parameters for the MPP portability problem. 3 First, a parallel solution using P processors can improve the best sequential solution by a factor of P, at most. Second, HPC problems tend to have third-or fourth-order complexity, and so parallel computation, while essential, offers only modest benefits. Third, "the whole force of parallelism must be transferred to the problem, not converted to 'heat' of implementational overhead."Researchers have addressed the portability problem periodically over the past 30 years, with well-known approaches involving language design, optimizing compilers, emulation, software engineering tools and methods, and function and application libraries. It is generally agreed that compromises are required: Either restrict the variety of architectures or scope of application, or bound expectations of performance or ease of implementation.

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“…To support the SCORE model, we employ a set of complementary design patterns -i.e., solutions to commonly recurring problems [25]. These particular patterns are presented here to better illuminate the nature of the SCORE model and our work on its implementation.…”

Section: Execution Patternsmentioning

confidence: 99%