Design principles for packet parsers

Abstract

All network devices must parse packet headers to decide how packets should be processed. A 64 × 10 Gb/s Ethernet switch must parse one billion packets per second to extract fields used in forwarding decisions. Although a necessary part of all switch hardware, very little has been written on parser design and the trade-offs between different designs. Is it better to design one fast parser, or several slow parsers? What is the cost of making the parser reconfigurable in the field? What design decisions most impact power and area?In this paper, we describe trade-offs in parser design, identify design principles for switch and router designers, and describe a parser generator that outputs synthesizable Verilog that is available for download. We show that i) packet parsers today occupy about 1-2% of the chip, and ii) while future packet parsers will need to be programmable, this only doubles the (already small) area needed.

Hardware-Software Co-Design for Network Performance Measurement

“…SRAM densities are now around 7000 Kb /mm 2 [13]. The smallest switching chips occupy 200 mm 2 [20]. Relative to these chips, a 32-Mbit cache in SRAM costs under 2.5% additional area, which we believe is reasonable.…”

“…These are already leveraged by applications like In-band Network Telemetry [6]. The set of packet headers in the schema-including standard headers, metadata and userdefined ones-can be parsed by a programmable switch parser [20]. The SELECT ... WHERE clause can be realized using a programmable match-action switch pipeline [17] that allows matches and actions on all parsable headers; on such pipelines, we can implement the WHERE predicate as the match condition.…”

“…We find that performance queries are feasible using a 32-Mbit SRAM cache, and a backing store that can support~802K cache evictions per second. These requirements can be easily met: a 32-Mbit SRAM cache occupies < 2.5% of the die area of a switching chip [20]), while scale-out key-value stores such as Memcached and Redis support a few hundred thousand operations per second per core [5,24,10, 1].…”

“…The recent emergence of programmable switching chips [2,15,7] suggests a change in thinking. Currently, however, these chips only support flexible packet parsing [20] and header processing [17]; their hardware primitives for measurement are still limited. Ideally, these chips would offer similar flexibility for network measurement as well.…”

Packet Transactions

“…Next, because no existing programmable switch supports the set of atoms required for our data-plane algorithms, we design a set of compiler targets for these algorithms based on Banzai ( §5.2). We show that these targets are feasible in a 32-nm standard-cell library with < 2% cost in area relative to a 200 mm 2 baseline switching chip [40]. Finally, we compile data-plane algorithms written in Domino to these targets ( §5.3) to show how a target's atoms determine the algorithms it can support.…”