Design Procedure for Integrated Microwave GaAs Stacked-FET High-Power Amplifiers

Abstract

The application of stacked-FETs in power amplifiers allows for a supply voltage higher than supported by the breakdown voltage of a single transistor. Potential benefits of the increased supply voltage are reduced supply currents and a lower matching ratio at the output of the amplifier. Furthermore, an increased output power per chip area is obtained due to the reduction in passive structures resulting in more area-efficient power combining. In this paper, the procedure for the design of integrated microwave stacked-FET is discussed. Several options for the correct distribution of RF voltage and current swings are investigated and the relationship between the number of stacked transistors and bandwidth is addressed. The procedure is demonstrated by the design of an S-band GaAs stacked-FET containing three transistors. This stacked-FET is applied in an S-band HPA that has a PAE of more than 40% at an output power of 20 W, which is more than twice the output power of any previously reported GaAs stacked-FET HPA.

Space-Compliant Design of a Millimeter-Wave GaN-on-Si Stacked Power Amplifier Cell through Electro-Magnetic and Thermal Simulations

“…For ISMN design, two different approaches are possible: a theoretical approach, where the analysis of the structure is carried out considering parasitics in order to find adequate design guidelines or formulas, as in [11,22,27], or a load-pull approach, where the (complex) optimum extrinsic load Z opt , gathered from load-pull simulations or measurements, is adopted for the design. In the theoretical approach, the values of the device parasitics must be known, extracted either from simulations or measurements [39], and some simplifying assumptions are usually made, neglecting some parasitics (e.g., inductive parasitics) and, above all, their non-linear behavior with input power (non-linear capacitances).…”

“…The most widely adopted ISMNs are shown in Figure 8: series inductance (L SERIES ) [10], feedback capacitance (C DS ) [38], shunt inductance (L SHUNT ) [43] and gate-source inductance (L GS ) [22]. Even if other solutions may exist [27], only these four possibilities are considered in this design, since they only require one additional component beyond C g . Note that both devices' loads depend on the external cell's load Z L , which thus represents a further degree of freedom.…”

“…In this design gate and drain voltages of the CS are −1.75 and 11.25 V, respectively, thus giving V G,CG = 9.5 V. Nevertheless, the assumption of equal drain-source DC voltages is valid only with no input power, or in small-signal conditions [12,27]. On the contrary, when the transistors are driven into compression, the DC components of the drain-source currents and consequently of the floating voltage V D,CS = V S,CG change.…”

“…In the literature, stacked PAs are largely exploited in CMOS technology [11][12][13][14][15][16][17][18], where the breakdown voltage is a major limit, but some examples can also be found in GaAs [19][20][21][22][23][24][25][26][27] and very few in GaN [28][29][30][31]. A main advantage of the stacked PA is that it can be profitably adopted as a basic high-power and high-gain cell to be further exploited in more complex PA architectures, from classical parallel combined PAs [32] to advanced architectures such as distributed PAs [33], spatially-combined PAs [34] and Doherty PAs [30,35].…”

Analysis of DC negative feedback mechanism in stacked power amplifiers

“…In this solution, the transistors are combined in series, resulting in a higher working voltage [3]. As a result, transistor stacking is wildly used in low-breakdown technologies, such as CMOS, GaAs and even GaN-on-Si [4,5,6,7]. Therefore, not only the AC characters but also the DC characters should be studied to make the stacked PAs work normally.…”