Design rule check and layout versus schematic for 3D integration and advanced packaging

Fischbach, Robert; Heinig, Andy; Schneider, Peter

doi:10.1109/3dic.2014.7152150

Cited by 2 publications

(1 citation statement)

References 7 publications

(6 reference statements)

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“…These models are also used to verify the reliability and performance of 3D interconnects in detail, e.g., for TSV arrays [98][99][100]. For the electrical domain, well-known techniques such as SPICE simulations, LVS or ERC verification are applied as well, but with additional consideration of 3D interconnects and multi-physics effects [101]. Some tools (e.g., Mentor Calibre) have also been tailored for this need.…”

Section: Multi-physics Simulation and Verificationmentioning

confidence: 99%

Physical Design Automation for 3D Chip Stacks

Knechtel¹,

Lienig²

2016

Proceedings of the 2016 on International Symposium on Physical Design

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The concept of 3D chip stacks has been advocated by both industry and academia for many years, and hailed as one of the most promising approaches to meet ever-increasing demands for performance, functionality and power consumption going forward. However, a multitude of challenges has thus far obstructed large-scale transition from "classical" 2D chips to stacked 3D chips. We survey major design challenges for 3D chip stacks with particular focus on their implications for physical design. We also derive requirements for advances in design automation, such as the need for a unified workflow. Finally, we outline current promising solutions as well as areas needing further research and development. bly design kit; design standards 2. 3D-CHIP STACKING OPTIONS AND HIGH-LEVEL DESIGN CHALLENGES 3D-chip stacking falls into four categories (Fig. 2): (i) package stacking, (ii) interposer stacks, (iii) through-silicon via (TSV)based 3D ICs, and (iv) monolithic 3D ICs. Each option has its This work is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike International 4.0 License.

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