Design Solutions for Sample-and-Hold Circuits in CMOS Nanometer Technologies

Abstract

Solutions for the design of low-voltage sample-andhold (S/H) circuits in CMOS nanometer technologies are presented. As a design example, a 0.8-V supply S/H is designed and simulated using a 130-nm CMOS process. It dissipates 0.5 mW at dc and provides almost a rail-to-rail signal swing. When clocked at 40 MS/s and with a 1.4-VPP differential input signal, the simulated spurious-free dynamic range, signal-to-noise ratio, and total harmonic distortion are 57, 67, and −56 dB (9 equivalent bits), respectively, with low sensitivity to supply, temperature, process, and mismatch variations. The proposed solution employs a three-stage low-voltage amplifier without a tail current source in the differential pair and a switch topology, which combines clock voltage doubling and dummy switches

Low-Voltage CMOS Switch for High-Speed Rail-To-Rail Sampling

“…It should be noted that switch size is constant for all Vdd voltages. Some additional simulations are done to compare between the proposed switch with bootstrapped NMOS switch (with dummy switch), [6], [13] and [26]. The simulation conditions for all schemes are the same.…”

A novel analog switch for high‐precision switched‐capacitor applications

“…2,3 As it can be seen in Figure 1, in this method, a dummy transistor is used to absorb the deposited channel charge of the main transistor. Using a dummy transistor is one of the earliest solutions to reduce the switch-induced errors.…”

“…The Equation 3 shows that for a simple MOS switch, the error ΔV is independent on input signal level; therefore, unlike to the charge injection error, the effect of the clock feedthrough on the holding capacitor is linear. The Equation 3 shows that for a simple MOS switch, the error ΔV is independent on input signal level; therefore, unlike to the charge injection error, the effect of the clock feedthrough on the holding capacitor is linear.…”

Input switch configuration for sample and hold circuits in low-voltage operation

“…The evolution of integrated circuit technologies, partially helps in meeting these requirements by continuously reducing the transistor channel length and oxide thickness. However, it brings new challenges, the most important of which is the decreasing supply voltage [2] [3].…”

“…In the literature, we can find several bootstrapped switch designs [3]- [9]. Each one was designed for a specific application with respect to a given technology.…”