Design Space Exploration of Partially Re-configurable Embedded Processors

Chattopadhyay,; Ahmed, M.F.; Karari,; Kammler,; Leupers,; Ascheid,; Meyr,

doi:10.1109/date.2007.364611

Cited by 17 publications

(15 citation statements)

References 12 publications

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“…Other related and complementary work includes: 1) use of local memories for improving the performance of custom instructions [25], [29]; 2) datapath merging [30] and combinational equivalence checking [31] techniques to improve resource sharing; 3) synthesis of custom instructions targeting field-programmable systems [32], [33], including support for run-time reconfiguration [34], [35]; and 4) transparent integration of custom instructions with a general-purpose processsor [36].…”

Section: Related Workmentioning

confidence: 99%

FISH: Fast Instruction SyntHesis for Custom Processors

Atasu

Luk

Mencer

et al. 2012

IEEE Trans. VLSI Syst.

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Abstract-This paper presents Fast Instruction SyntHesis (FISH), a system that supports automatic generation of custom instruction processors from high-level application descriptions to enable fast design space exploration. FISH is based on novel methods for automatically adapting the instruction set to match an application in a high-level language such as C or C. FISH identifies custom instruction candidates using two approaches: 1) by enumerating maximal convex subgraphs of application data flow graphs and 2) by integer linear programming (ILP). The experiments, involving ten multimedia and cryptography benchmarks, show that our contributed algorithms are the fastest among the state-of-the-art techniques. In most cases, enumeration takes only milliseconds to execute. The longest enumeration run-time observed is less than six seconds. ILP is usually slower than enumeration, but provides us with a complementary solution technique. Both enumeration and ILP allow the use of multiple different merit functions in the evaluation of data-flow subgraphs. The experiments demonstrate that, using only modest additional hardware resources, up to 30-fold performance improvement can be obtained with respect to a single-issue base processor.

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Section: Related Workmentioning

confidence: 99%

FISH: Fast Instruction SyntHesis for Custom Processors

Atasu

Luk

Mencer

et al. 2012

IEEE Trans. VLSI Syst.

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“…The recent work in this regard is [14]. But it describes only fine grain reconfigurable architecture with static reconfiguration.…”

Section: Weaknesses Of Lisatekmentioning

confidence: 99%

Application Specific Processors for Multimedia Applications

Rashid

Apvrille

Pacalet

2008

2008 11th IEEE International Conference on Computational Science and Engineering

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A well-known challenge during processor design is to obtain best possible results for a typical target application domain by combining flexibility and computational performance. ASIPs (Application Specific Instruction Set Processors) provide a tradeoff between generality of processor (flexibility) and its physical characteristics (computational performance and silicon area).This paper evaluates an ASIP design methodology based on the extension of an existing instruction set and architecture described with LISA 2.0 language. The objective is to accelerate the ASIPs design process by using partially predefined, configurable RISC-like embedded processor cores that can be quickly tuned to given applications by means of ISE (Instruction Set Extension) techniques. A case study demonstrates the methodological approach for the JPEG algorithm and motion estimation encoding algorithm of H.264 encoding standard.

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“…ASIPs are flexible within an application domain, being able to accomplish a group of functionalities using a set of common operations. ASIP designs have been proposed in literature for motion estimation [1,4], Viterbi or LDPC channel coding/decoding [2,3], GNSS receiver [6], Discrete Cosine Transform [8], Fast Fourier Transform [7,8], and cryptography [9]. Since they are optimized towards certain applications, ASIPs combine the high performance and efficiency of a dedicated solution with the flexibility of a programmable solution.…”

Section: Introductionmentioning

confidence: 99%

“…In the most recent panorama [1][2][3][4][5][6][7][8][9][10][11][12] of digital processing systems, the design of application specific instruction-set processors (ASIPs) is gaining ground to fill the gap between ASICs and DSPs. ASIPs are flexible within an application domain, being able to accomplish a group of functionalities using a set of common operations.…”

Section: Introductionmentioning

confidence: 99%

ASIP-based reconfigurable architectures for power-efficient and real-time image/video processing

Saponara

Casula

Fanucci

2008

J Real-Time Image Proc

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To meet both flexibility and performance requirements, particularly when implementing high-end real-time image/video processing algorithms, the paper proposes to combine the application specific instruction-set processor (ASIP) paradigm with the reconfigurable hardware one. As case studies, the design of partially reconfigurable ASIP (r-ASIP) architectures is presented for two classes of algorithms with widespread diffusion in image/video processing: motion estimation and retinex filtering. Design optimizations are addressed at both algorithmic and architectural levels. Special processor concepts used to trade-off performance versus flexibility and to enable new features of post-fabrication configurability are shown. Silicon implementation results are compared to known ASIC, DSP or reconfigurable designs; the proposed r-ASIPs stand for their better performance-flexibility figures in the respective algorithmic class

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Design Space Exploration of Partially Re-configurable Embedded Processors

Cited by 17 publications

References 12 publications

FISH: Fast Instruction SyntHesis for Custom Processors

FISH: Fast Instruction SyntHesis for Custom Processors

Application Specific Processors for Multimedia Applications

ASIP-based reconfigurable architectures for power-efficient and real-time image/video processing

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