Design techniques for high-throughput BiCMOS self-timed SRAMs

A novel stability and process sensitivity driven model for optimal sized FinFET based SRAM

“…In order to obtain higher noise margin along with better performance, modification in cell topologies are done. Various 7T, 8T and 9T single ended and differential SRAM cells have been introduced to meet the future SRAM requirements at the cost of area [16][17][18][19][20]. In addition to this, subthreshold mode of operation is introduced to accomplish low power design criteria, where the devices operate at below threshold voltage [2].…”