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Chip ArchitectureThis paper introduces a 156M-b/s x 6 time/space switch LSI for SDH cross-connect systems. To minimize 1/0 power consumption, we implemented a low-power differential CMOS 1/0 circuit which can apply to up to 6~22-Mb/s data transmission. The chip was designed by using a silicon compilation tool and fabricated using 0.5-pm CMOS process technology. Functions up to 300-Mb/s 1/0 operation and 0.9-W total power consumption have been confirmed. This chip uses a 208-pin plastic QFP with a multi layer lead structure. Fig. 1 shows a block diagram of the time/space switch. This chip accommodates six highways of STM-1 (1 56-Mb/s) and interchanges time-slots within and between input time-divided multiplex si,gnals. The input signal (1% Mb/s) from the input ports is converted to 3-parallel bite data Control Logic 7 1 ACM ( dual-port RAM )