A 333 MHz, 72 Kb BiCMOS pipelined buffer memory with built-in self test

Yokomizo, Koichi; Naito, K.

doi:10.1109/vlsic.1992.229250

Cited by 3 publications

(1 citation statement)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…High-speed embedded memories require built-in self-test (BIST) circuitry to thoroughly test the memory at speed [1]. Although high-speed self-test circuits for memories exist, most have been dependent upon pseudorandom patterns [2]. This approach can be helpful in finding non-target-type defects [3] but, for well-understood defect sets, deterministic test patterns are superior.…”

Section: Introductionmentioning

confidence: 99%

A 370-MHz memory built-in self-test state machine

Adams¹,

Connor²,

Koch³

et al.

Proceedings the European Design and Test Conference. ED&TC 1995

View full text Add to dashboard Cite

Hardware and simulation results for a 370-MHz memory built-in self-test state machine are presented. Dynamic differential cascode voltage switch logic, unique clocking techniques, and logic pipelining were used to achieve the 370-MHz performance. Testing of multiple SRAMs and content addressable memories is accomplished with deterministic patterns generated by the state machine. Inclusion of a programmable pattern implemented via scan initialization provides test-pattern flexibility. Failing addresses are stored for redundancy implementation.

show abstract

Section: Introductionmentioning

confidence: 99%