Proceedings 2001 Conference on Advanced Research in VLSI. ARVLSI 2001
DOI: 10.1109/arvlsi.2001.915549
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Design, verification, and test of a true single-phase 8-bit adiabatic multiplier

Suhwan Kim
1
,
C.I. Ziesler
2
,
Marios C. Papaefthymiou
3
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Cited by 5 publications
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Multiplier Energy Reduction by Dynamic Voltage Variation

Moshnyaga
1
,
Yamanaka
2
2005
IEICE Transactions on Fundamentals of Electronics, Communicatio
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Multiplier Energy Reduction by Dynamic Voltage Variation

Moshnyaga
1
,
Yamanaka
2
2005
IEICE Transactions on Fundamentals of Electronics, Communicatio
1
0
1
0
View full textAdd to dashboardCite

Resonant clocking using distributed parasitic capacitance

Drake
1
,
Nowka
2
,
Nguyen
3
et al.
Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003.
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A true single-phase 8-bit adiabatic multiplier

Kim
1
,
Ziesler
2
,
Papaefthymiou
3
2001
Proceedings of the 38th Conference on Design Automation - DAC '01
22
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9
0
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