Designer Ge quantum dots on Si: A heterostructure configuration with enhanced optoelectronic performance

Kuo, Ming-Hao; Wang, C. C.; Lai, Wei-Ting; George, T. Adrian; Li, Peiwen

doi:10.1063/1.4768292

Cited by 26 publications

(58 citation statements)

References 29 publications

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“…Considering the work functions for Al (4.16 eV), NiGe (5.2 eV), Ge (4.33 eV), and SiGe (4.55 eV) and the gate oxide thickness of 3-4 nm, our experimental observations of negative Vfb suggest estimated positive fixed charge densities of ~5 × 10 11 cm −2 at interfaces of SiO2/SiGe and SiO2/Ge dot. It is interesting to note that the positive fixed charges measured for our NiGe/SiO2/SiGe and Al/SiO2/Ge-dot/SiO2/SiGe MOS capacitors are in contrast to the conventional expectation of negative fixed charges produced by the thermal oxidation of SiGe alloys (LeGoues et al, 1989;Nayak et al, 1990Nayak et al, , 1992 or at high-k dielectric/Ge interfaces generated either by chemical vapor deposition or atomic layer deposition (Bai et al, 2005;Zhang et al, 2006;Deng et al, 2011) As described in our previous reports (Kuo et al, 2012;Lai et al, 2015), the interfacial SiO2 layer between the Ge dot and the SiGe shell is formed by the thermal oxidation of Si interstitials that are released from the Si substrate. The oxide layer between the Ge dot and the deposited Al gate is formed by the thermal oxidation of Si interstitials that migrate along the surface of Ge dot to its distal end.…”

Section: Discussionmentioning

confidence: 67%

“…Our previous results (Chien et al, 2011;Kuo et al, 2012;Wang et al, 2013;Chen et al, 2014;Lai et al, 2015) have shown that thermal oxidation performed on poly-Si0.85Ge0.15 nano-pillar structures preferentially converts the Si from the poly-Si0.85Ge0.15 to SiO2, leading to the formation of a single Ge dot within each oxidized nano-pillar through an unusual Ostwald Ripening process consolidating the segregated Ge nanocrystallites (Chien et al, 2011). Interestingly, excess thermal oxidation (or thermal annealing) of 15-65 min enables the as-formed Ge dot to penetrate the underlying, buffer Si3N4 layer, and ultimately form a 2-15-nm-thick Si1−xGex-shell layer (x > 0.5) with a "cup"-shape morphology near the top surface of the Si substrate when the Ge dot comes in close proximity to the Si substrate.…”

Section: Resultsmentioning

confidence: 99%

“…Our previously reports (Kuo et al, 2012;Chen et al, 2014;Lai et al, 2015) have described that the interfacial SiO2 thickness is determined by an exquisitely controlled dynamic balance that exists between the fluxes of oxygen and Si interstitials. Thus, judicial control of either the source of Si interstitials or the flux of oxygen interstitials by changing thermal annealing conditions during the penetration of Ge dot effectively controls the interfacial SiO2 thickness.…”

Section: Discussionmentioning

confidence: 99%

“…Recently, we have demonstrated a unique MOS gate-stack structure for Ge MOS devices consisting of a self-organized SiO2/ Ge-dot/SiO2/SiGe-shell over the Si substrate that is achieved in a single fabrication step (Chien et al, 2011;Kuo et al, 2012Kuo et al, , 2015Wang et al, 2013;Chen et al, 2014;Lai et al, 2015). Our approach is primarily based on the exquisite control available through lithographic patterning combined with the selective oxidation of Si1−xGex nano-pillars over buffer layers of Si3N4 deposited over the Si substrates.…”

Section: Ge-based Mos Gate-stack Engineeringmentioning

confidence: 99%

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Gate-Stack Engineering for Self-Organized Ge-dot/SiO2/SiGe-Shell MOS Capacitors

et al. 2016

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We report the first-of-its-kind, self-organized gate-stack heterostructure of Ge-dot/ SiO2/SiGe-shell on Si fabricated in a single step through the selective oxidation of a SiGe-nanopatterned pillar over a Si3N4 buffer layer on a Si substrate. Process-controlled tunability of the Ge-dot size (7.5-90 nm), the SiO2 thickness (3-4 nm), and the SiGeshell thickness (2-15 nm) have been demonstrated, enabling a practically achievable core building block for Ge-based metal-oxide-semiconductor (MOS) devices. Detailed morphologies, structural, and electrical interfacial properties of the SiO2/Ge-dot and SiO2/SiGe interfaces were assessed using transmission electron microscopy, energy dispersive X-ray spectroscopy, and temperature-dependent high/low-frequency capacitance-voltage measurements. Notably, NiGe/SiO2/SiGe and Al/SiO2/Ge-dot/SiO2/SiGe MOS capacitors exhibit low interface trap densities of as low as 3-5 × 10 11 cm −2 eV −1 and fixed charge densities of 1-5 × 10 11 cm −2, suggesting good-quality SiO2/SiGe-shell and SiO2/Ge-dot interfaces. In addition, the advantage of having single-crystalline Si1−xGex shell (x > 0.5) in a compressive stress state in our self-aligned gate-stack heterostructure has great promise for possible SiGe (or Ge) MOS nanoelectronic and nanophotonic applications.

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Section: Discussionmentioning

confidence: 67%

Section: Resultsmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

Section: Ge-based Mos Gate-stack Engineeringmentioning

confidence: 99%

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Gate-Stack Engineering for Self-Organized Ge-dot/SiO2/SiGe-Shell MOS Capacitors

et al. 2016

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“…The SiGe pillar density is approximately 1 × 10 9 cm −2 over the buffer Si 3 N 4 layers. Next, the nanopatterned structure is subjected to thermal oxidation at 900 °C within an H 2 O ambient producing 90-nm diameter, spherical Ge QDs that migrate into the buffer Si 3 N 4 layer [17, 18], as shown in Fig. 1a.…”

Section: Methodsmentioning

confidence: 99%

A Unique Approach to Generate Self-Aligned SiO2/Ge/SiO2/SiGe Gate-Stacking Heterostructures in a Single Fabrication Step

et al. 2015

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We report a first-of-its-kind, unique approach for generating a self-aligned, gate-stacking heterostructure of Ge quantum dot (QD)/SiO2/SiGe shell on Si in a single fabrication step. The 4-nm-thick SiO2 layer between the Ge QD and SiGe shell fabricated during the single-step process is the result of an exquisitely controlled dynamic balance between the fluxes of oxygen and silicon interstitials. The high-quality interface properties of our “designer” heterostructure are evidenced by the low interface trap density of as low as 2–4 × 1011 cm−2 eV−1 and superior transfer characteristics measured for Ge-based metal-oxide-semiconductor field-effect transistors (MOSFETs). Thanks to the very thin interfacial SiO2 layer, carrier storage within the Ge QDs with good memory endurance was established under relatively low-voltage programming/erasing conditions. We hope that our unique self-aligned, gate-stacking heterostructure provides an effective approach for the production of next-generation, high-performance Ge gate/SiO2/SiGe channel MOSFETs.

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The amazing world of self-organized Ge quantum dots for Si photonics on SiN platforms

et al. 2023

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Beginning with our exciting discovery of germanium (Ge) spherical quantum-dot (QD) formation via the peculiar and symbiotic interactions of Si, Ge, and O interstitials, we have embarked on a journey of vigorous exploration, creating unique configurations of self-organized Ge-QDs/Si-containing layers. Our aim is to generate advanced Ge-QD photonic devices, while using standard, mainstream Si processing techniques. This paper summarizes our portfolio of innovative Ge-QD configurations. With emphasis on both controllability and repeatability, we have fabricated size-tunable, spherical Ge-QDs that are placed at predetermined spatial locations within Si-containing layers (SiO2, Si3N4, and Si) using a coordinated combination of lithographic patterning and self-assembled growth. We have successfully exploited the multi-dimensional, parameter spaces of process conditions in combination with layout designs to achieve exquisite control available through the thermal oxidation of lithographically patterned, poly-Si1 − xGex structures in close proximity with Si3N4/Si layers. In so doing, we have gained insight into the growth kinetics and formation mechanisms of self-organized, Ge spherical QDs embedded within SiO2, Si3N4, and Si layers, respectively. Our Ge-QD configurations have opened up a myriad of process/integration possibilities including top-to-bottom evanescent-wave coupling structures for SiN-waveguided Ge-QD photodetectors and Ge-QD light emitters for Si photonics within Si3N4 integrated photonics platforms for on-chip interconnects and sensing.

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Designer Ge quantum dots on Si: A heterostructure configuration with enhanced optoelectronic performance

Cited by 26 publications

References 29 publications

Gate-Stack Engineering for Self-Organized Ge-dot/SiO2/SiGe-Shell MOS Capacitors

Gate-Stack Engineering for Self-Organized Ge-dot/SiO2/SiGe-Shell MOS Capacitors

A Unique Approach to Generate Self-Aligned SiO2/Ge/SiO2/SiGe Gate-Stacking Heterostructures in a Single Fabrication Step

The amazing world of self-organized Ge quantum dots for Si photonics on SiN platforms

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