Designing high-power limiter circuits with GaAs PIN diodes

Smith, D.G.; Heston, D.D.; Allen, D.L.

doi:10.1109/mwsym.1999.779486

Cited by 36 publications

(9 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Under the condition of small-signal, the off-state diodes load the RF path by their parasitics, thus, the limiter should be designed for a minimum insertion loss so as not to degrade the overall NF of the circuit. Conventionally, a number of diodes are placed in seriesconnection to reduce the capacitance [12], where more diodes are used at the input than those at the output in order to reduce the capacitance at the cost of increased output power. In this paper, two-stage PIN-limiter topology is proposed as shown in Fig.…”

Section: A Design Of the Pin-diode Based Limitermentioning

confidence: 99%

“…For PIN-diodes, both the insertion loss and the maximum working frequency are a function of the parasitic capacitance that is proportional to the diode area. Meanwhile, it has been reported that the power-handling capability of a GaAs PIN-diode is proportional to its perimeter [12]. In order to reduce the insertion loss and increase the bandwidth of the limiter, we adopt an oval-shape diode geometry for the larger sized PIN diode, which can reduce the diode area of more than 50% compared with the round diode of equivalent perimeter [22].The integrated two-stage PIN-diode based limiter, three-stage LNA and an equalizer is designed and implemented by using the combined PIN/0.15-µm-pHEMT technology.…”

Section: A Fabrication Of Device and Circuitmentioning

confidence: 99%

See 1 more Smart Citation

Codesign of ${K}$ a-Band Integrated GaAs PIN Diodes Limiter and Low Noise Amplifier

Yang

Rong

et al. 2019

IEEE Access

View full text Add to dashboard Cite

In this paper, a novel concurrent design of integrated PIN-diode based limiter and low noise amplifier (LNA) is presented for Ka-band MMICs fabricated using a combined PIN/0.15-µm-pHEMT technology. To improve the small-signal performance and the power-handling capability of the limiter-LNA, the improvement of the PIN-limiter circuit structure and the survivability of the LNA network are proposed. In addition, the total chip area is 2.5 mm × 1.2 mm with an equalizer integrated on chip behind the limiter-LNA to improve the bandwidth with a minimum impact on overall NF. The measurements show that the proposed limiter-LNA with only two-stage limiter structure tolerates up to 38 dBm continuous wave (CW) input power without failure, and the average gain and the noise figure for the limiter-LNA are 17 dB and 2.2-2.6 dB, respectively, on the 30-38 GHz frequency bandwidth. INDEX TERMS GaAs pHEMT, integrated limiter low noise amplifier (LNA), MMIC, noise figure (NF), PIN diode.

show abstract

Section: A Design Of the Pin-diode Based Limitermentioning

confidence: 99%

Section: A Fabrication Of Device and Circuitmentioning

confidence: 99%

Codesign of ${K}$ a-Band Integrated GaAs PIN Diodes Limiter and Low Noise Amplifier

Yang

Rong

et al. 2019

IEEE Access

View full text Add to dashboard Cite

show abstract

“…Power limiters are also implemented in a diverse array of technologies including semiconductor diode [6], [7], FET [8]- [10], ferromagnetic [11]- [13], MEMS [14], [15], and plasma [16]- [20]. Power limiting is important for the protection of sensitive RF and microwave systems.…”

Section: Introductionmentioning

confidence: 99%

Plasma-Based Power Limitation for Highly Linear MEMS Switch Protection and Isolation Enhancement

2020

View full text Add to dashboard Cite

A novel hybrid approach integrating a MEMS switch with a gas discharge tube plasma cell to enhance switch survivability and isolation, especially at high incident power levels, is demonstrated. The theory of operation is discussed including consideration of the underlying plasma phenomena as well as the practical integration details. Measurement of a fabricated prototype is presented. Discussion of measurement challenges and potential solutions is accompanied by detailed explanations of measurement practice. Measurements provide insights into applied RF plasmas not present in the body of literature. Wideband enhancement of isolation by more than 10 dB at 50 W incident power is observed in a quasi-absorptive mode with increasing isolation over power. No penalty to the excellent linearity of MEMS switches is detected with a measured IIP3 of 75.3 dBm. Advantages in linearity as compared to semiconductor-based power limiting solutions are shown and demonstrate state-of-the-art performance. An incremental insertion loss of less than 0.2 dB with a return loss better than 12.5 dB is reported. Measurement of the effects on MEMS switch timing parameters as well as time domain characterization of the plasma breakdown is included.

show abstract

“…Diode-stacking can also reduce the capacitance but adversely increases the turn-on threshold [5]. Removing part of the PIN junction area using mesa construction can reduce the parasitic capacitance but detrimentally increases the diode's transient thermal impedance [ 6 ].…”

Section: Introductionmentioning

confidence: 99%

Limiting and transient performances of a low loss PIN-Schottky limiter

Lim¹

2013

2013 IEEE International RF and Microwave Conference (RFM)

View full text Add to dashboard Cite

The main cause of loss in the PIN-Schottky limiter is the diodes' parasitic capacitances. Techniques to counter the parasitic capacitances include using bare chip, air cavity packaging, diode stacking, mesa construction, isolating the Schottky diode from the signal path and connecting the diodes to a low impedance node. But the aforementioned techniques either sacrifice cost, manufacturability, size, performances or thermal ruggedness. To reduce loss in the PIN-Schottky limiter, we re-configured its parasitics into a low pass ladder network. This paper reports on the new configuration's changed large signal and transient performances. We observed improved isolation at 0.9 and 2.4 GHz, and a beneficial reduction in the initial energy that slips through the limiter before limiting begins. In conclusion, this configuration simultaneously improves insertion loss, matching, isolation and spike leakage suppression. It has the potential to improve limiting performances in wideband receivers for wireless communication and medical imaging.

show abstract

Designing high-power limiter circuits with GaAs PIN diodes

Cited by 36 publications

References 1 publication

Codesign of ${K}$ a-Band Integrated GaAs PIN Diodes Limiter and Low Noise Amplifier

Codesign of ${K}$ a-Band Integrated GaAs PIN Diodes Limiter and Low Noise Amplifier

Plasma-Based Power Limitation for Highly Linear MEMS Switch Protection and Isolation Enhancement

Limiting and transient performances of a low loss PIN-Schottky limiter

Contact Info

Product

Resources

About