Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints

Gilabert, Francisco Jurado; Ludovici, Daniele; Medardoni, Simone; Bertozzi, Davide; Benini, Luca; Gaydadjiev, Georgi

doi:10.1109/cisis.2009.30

Cited by 22 publications

(10 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This way, overall area and performance figures can be drawn. Differently from our previous work in [2], the simulator has been enhanced with the implementation of dualclock FIFO interfaces thus enabling the modeling of systems where cores and network are completely decoupled from the frequency viewpoint. Interestingly, achieved results may look counterintuitive at a first glance when compared with commonly known theoretical properties of the investigated topologies.…”

Section: Related Workmentioning

confidence: 99%

“…Our previous work in [2,3,5] presented silicon-aware topology analysis and comparison for networks with 16 nodes. In all these works, the exploration of the design space is performed through a transaction-level simulation environment that is able to back-annotate key parameters (frequency, latency, area) from the results of physical synthesis.…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology

Ludovici

Gaydadjiev

Gilabert

et al. 2010

Proceedings of the Third International Workshop on Network on Chip Architectures

View full text Add to dashboard Cite

Nowadays, system designers have adopted Networks-on-Chip as communication infrastructure of general-purpose tile-based Multi-Processor System-on-Chip (MPSoC). Such decision implies that a certain topology has to be selected to efficiently interconnect many cores on the chip. To ease such a choice, the networking literature offers a plethora of works about topology analysis and characterization for the off-chip domain. However, theoretical parameters and many intuitive assumptions of such off-chip networks do not necessarily hold when a topology is laid out on a 2D silicon surface. This is due to the distinctive features of silicon technology design pitfalls. This work is a first milestone to bridge this gap, in fact, we propose a comprehensive analysis framework to assess k-ary n-mesh and C-mesh topologies at different level of abstractions, from system to layout level, while capturing implications of system and layout parameters across design hierarchy. When a certain topology proves to be slow due to long links crossing the chip, pipeline stages have been inserted to cope with such slow-down. Furthermore, costs of such speed-up technique have been evaluated to draw a comprehensive performance/area figure.The gap between the constraints driving the design of onchip vs. off-chip interconnection networks (and hence the gap between the final network architectures selected for use in each domain) is increasingly widening even more as an effect of the relentless pace of technology scaling to the nanoscale regime. New physical effects come into play and may either degrade performance/power in an unpredictable way or even affect feasibility of the design at hand or of specific architecture design techniques.Examples concern the large buffering cost associated with techniques borrowed from the off-chip domain (e.g., for congestion management strategies or for deadlock-free and multicast friendly switching mechanisms) which are not affordable in the on-chip domain. Moreover, the interconnect reverse scaling is making designs for on-chip integration increasingly interconnect-dominated, due to the delay associated with the shrinking cross-section area of on-chip interconnects. This effect becomes increasingly severe at each technology node and tends to widen the gap between post-synthesis and postplace&route performance figures and even to move critical path delays from logic blocks to large global wires.Selection of the topology connectivity pattern in the early stages of network design is a decision which is extremely sensitive to both the effects illustrated above. In fact, topologies for on-chip networks must match the 2D silicon surface, while off-chip realizations are dictated by board/rack organization. The 2D mapping constraint raises implementation issues such as wire crossings, wires of uneven length or the decrease of switch operating frequency with the number of I/O ports. As an ultimate consequence, topologies borrowed from off-chip networks should be reassessed in the on-chip environment and validated against...

show abstract

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology

Ludovici

Gaydadjiev

Gilabert

et al. 2010

Proceedings of the Third International Workshop on Network on Chip Architectures

View full text Add to dashboard Cite

show abstract

“…Our previous implementation effort in 65nm technology of NoC topology layouts indicated that when wiring is considered, the delay of inter-switch links causes a significant performance drop for most regular NoC topologies depending on their connectivity pattern [18].…”

Section: A Baseline Vc-less Switchmentioning

confidence: 99%

Improved Utilization of NoC Channel Bandwidth by Switch Replication for Cost-Effective Multi-processor Systems-on-Chip

Gilabert

Gómez

Medardoni

et al. 2010

2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip

Self Cite

View full text Add to dashboard Cite

Virtual channels are an appealing flow control technique for on-chip interconnection networks (NoCs), in that they can potentially avoid deadlock and improve link utilization and network throughput. However, their use in the resource constrained multi-processor system-on-chip (MPSoC) domain is still controversial, due to their significant overhead in terms of area, power and cycle time degradation. This paper proposes a simple yet efficient approach to VC implementation, which results in more area- and power-saving solutions than conventional design techniques. While these latter replicate only buffering resources for each physical link, we replicate the entire switch and prove that our solution is counter intuitively more area/power efficient while potentially operating at higher speeds. This result builds on a well-known principle of logic synthesis for combinational circuits (the area-performance trade-off when inferring a logic function into a gate-level netlist), and proves that when a designer is aware of this, novel architecture design techniques can be conceived

show abstract

“…Several NoC platforms and related design concepts have been published during the recent years: [3], [4], [5], and [6], among others. The dependability issue in the context with NoCs is raising interest in research in the recent years.…”

Section: Dependable Soc Communication Architecturesmentioning

confidence: 99%

Invited paper: Design criteria for dependable System-on-Chip architectures

Hollstein

Samman

Jaiswal

et al. 2011

6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)

View full text Add to dashboard Cite

The rapid improvement of semiconductor technologies is the enabling factor for the design of large-scale Systemon-Chip (SoC) architectures. At the same time the scale-down of feature sizes in silicon technologies brings up new challenges as parameter variations of the transistor devices, an increased vulnerability for wear-out effects during the lifetime of the device and increased sensitivity for soft-errors. The overall system reliability is therefore an important topic to be addressed in the SoC design process as well as economic considerations related to manufacturing yield and lifetime maintainability. The aim of this contribution is to outline implications for the design process and to illustrate the dependability aspects at the example of SoC communication architectures being implemented as Networkson-Chip (NoCs).

show abstract

Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints

Cited by 22 publications

References 16 publications

Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology

Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology

Improved Utilization of NoC Channel Bandwidth by Switch Replication for Cost-Effective Multi-processor Systems-on-Chip

Invited paper: Design criteria for dependable System-on-Chip architectures

Contact Info

Product

Resources

About