2007
DOI: 10.1109/tcsi.2007.907864
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Designs for Ultra-Tiny, Special-Purpose Nanoelectronic Circuits

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Cited by 37 publications
(27 citation statements)
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“…To realize the nanoFSM, we adopt a bottom-up compatible strategy using common circuit modules or tiles that are interconnected and programmed for distinct logic functions (21,22). This strategy contrasts conventional circuit designs, which require different layouts for the distinct logic elements.…”
Section: Resultsmentioning
confidence: 99%
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“…To realize the nanoFSM, we adopt a bottom-up compatible strategy using common circuit modules or tiles that are interconnected and programmed for distinct logic functions (21,22). This strategy contrasts conventional circuit designs, which require different layouts for the distinct logic elements.…”
Section: Resultsmentioning
confidence: 99%
“…1B consists of two programmable nanowire transistor arrays, where each cross-point in the arrays corresponds to a programmable transistor node having an active (transistor) or inactive (resistor) state. The output of the first array serves as the input to the second array such that the two-level NOR-logic structure of each tile can be programmed to yield complete Boolean logic (21,22), and thus the necessary arithmetic and register elements of the nanoFSM.…”
Section: Resultsmentioning
confidence: 99%
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“…[3][4][5]19,20 To this end, we recently introduced a dielectric charge-trapping shell structure on nanowire transistor elements and showed that by modulating the charge state in the dielectric layers the transistor could be programmed as "active" or "inactive" within a specific logic window. Integration of these nanowire device elements into a crossbar array 19,20 further yielded a basic module or tile that could be used for proposed array-based architecture.…”
mentioning
confidence: 99%