Determination of key parameters for SEU occurrence using 3-D full cell SRAM simulations

Roche, Ph.; Palau, J.M.; Bruguier, G.; Tavernier, C.; Ecoffet, R.; Gasiot, J.

doi:10.1109/23.819093

Cited by 122 publications

(50 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Similar results have been found in previous works for a temperature up to 418K [7], [12]. This behavior can be explained for the maximum current amplitude I, by the average of the electron mobility µ [13]:…”

Section: Ii1-simulation Of a Single Soi Nmos Transistorsupporting

confidence: 76%

Compact modeling of the high temperature effect on the single event transient current generated by heavy ions in SOI 6T-SRAM

Boufouss

Pulido

Flandre

2010

Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT)

View full text Add to dashboard Cite

A temperature dependence analysis of the single event transient current induced by heavy ions irradiation is performed in the range of 300K to 500K on a 1μm SOI CMOS MOSFET standard 6T-SRAM cell. The Sentaurus TCAD mixedmode numerical simulation showed a significant impact of the temperature on the current induced by the radiation and as a result, an increase of the 6T-SRAM sensitivity upon radiation. A SOI MOSFET compact model introduced in SPICE as a Verilog-A module reproducing the single event effects was developed. This model shows a very good agreement with the TCAD simulations results but with a drastic reduction of the simulation time. Furthermore this model could be extended to other circuits simulations. This result is of importance to allow for extensive circuit design studies which cannot be carried out with TCAD physical simulations.

show abstract

Section: Ii1-simulation Of a Single Soi Nmos Transistorsupporting

confidence: 76%

Compact modeling of the high temperature effect on the single event transient current generated by heavy ions in SOI 6T-SRAM

Boufouss

Pulido

Flandre

2010

Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT)

View full text Add to dashboard Cite

show abstract

“…A simplified model was proposed by Roche et al in [4], using 3D device simulations in 0.35μm technology. According to their definition, Q crit can be found using:…”

Section: Ion Current Models For Q Crit Characterizationmentioning

confidence: 99%

Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAM

Naseer

Boulghassoul

Draper

et al. 2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

Abstract-Due to continuous technology scaling, the reduction of nodal capacitances and the lowering of power supply voltages result in an ever decreasing minimal charge capable of upsetting the logic state of memory circuits. In this paper we investigate the critical charge (Q crit ) required to upset a 6T SRAM cell designed in a commercial 90nm process. We characterize Q crit using different current models and show that there are significant differences in Q crit values depending on which models are used. Discrepancies in critical charge characterization are shown to result in under-predictions of the SRAM's associated soft error rate as large as two orders of magnitude. For accurate Q crit calculation, it is critical that 3D device simulation is used to calibrate the current pulse modeling heavy ion strikes on the circuit, since the stimuli characteristics are technology feature size dependant. Current models with very fast characteristic timing parameters are shown to result in conservative soft error rate predictions; and can assertively be used to model ion strikes when 3D simulation data is not available.

show abstract

“…Because of the single event particle strike at a sensitive location in the SRAM (typically the drain of the OFF NMOS transistor), charge collected at the junction results in a cur- [9]. However, during the particle-strike, the voltage changes so rapidly that it is unreasonable to assume that the NMOS transistor of the feedback inverter would be able to respond in a quasistatic manner.…”

Section: ¿º½ × ù×× óòmentioning

confidence: 99%

Evaluation of non-quasi-static effects during SEU in deep-submicron MOS devices and circuits

Jain

Kumar

Vasi

et al. 2006

19th International Conference on VLSI Design Held Jointly With 5th International Conference on Embedded Systems Design (VLSID'0

View full text Add to dashboard Cite

show abstract

Determination of key parameters for SEU occurrence using 3-D full cell SRAM simulations

Cited by 122 publications

References 12 publications

Compact modeling of the high temperature effect on the single event transient current generated by heavy ions in SOI 6T-SRAM

Compact modeling of the high temperature effect on the single event transient current generated by heavy ions in SOI 6T-SRAM

Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAM

Evaluation of non-quasi-static effects during SEU in deep-submicron MOS devices and circuits

Contact Info

Product

Resources

About