Development and characterization of new generation panel fan-out (P-FO) packaging technology

Chang, Hong-Da; Chang, David; Liu, Kenny; Hsu, H. S.; Tai, Rui-Feng; Huang, Hsiao-Chun; Lai, Yi-Che; Lu, Chang-Lun; Lin, Chun-Tang; Chiu, Steve

doi:10.1109/ectc.2014.6897402

Cited by 38 publications

(1 citation statement)

References 4 publications

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“…Starting from ECTC2013, Fraunhofer have been presenting their evaluation results on compression molding of a large area (610 mm Â 457 mm) FOPLP [40][41][42]. At ECTC2014, SPIL published two papers on FOPLP called P-FO, one is to develop and characterize a 370 mm Â 470 mm [43] and the other is to measure their warpage [44]. One of the bottlenecks for FOPLP is the availability of panel equipment such as the spin coating, physical vapor deposition (PVD), electrochemical deposition (ECD), etching, backgrinding, solder ball mounting, and dicing for making the molds, RDLs, and packages, due to the lack of the standard of panel sizes.…”

Section: Introductionmentioning

confidence: 99%

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Lau

2019

Journal of Electronic Packaging

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The recent advances and trends in fan-out wafer/panel-level packaging (FOW/PLP) are presented in this study. Emphasis is placed on: (A) the package formations such as (a) chip first and die face-up, (b) chip first and die face-down, and (c) chip last or redistribution layer (RDL)-first; (B) the RDL fabrications such as (a) organic RDLs, (b) inorganic RDLs, (c) hybrid RDLs, and (d) laser direct imaging (LDI)/printed circuit board (PCB) Cu platting and etching RDLs; (C) warpage; (D) thermal performance; (E) the temporary wafer versus panel carriers; and (F) the reliability of packages on PCBs subjected to thermal cycling condition. Some opportunities for FOW/PLP will be presented.

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