Development and demonstration of equivalent material characteristics for microbump arrays utilized in failure estimation of chip-on-chip packaging

Lee, Chang‐Chun; Huang, Pei‐Chen; Chian, Bow-Tsin

doi:10.1109/itherm.2016.7517559

Cited by 3 publications

(1 citation statement)

References 20 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Besides, the equivalent structural properties of TSV were studied by Che et al [24], [25] for the wafer-level warpage and stress analysis by assuming a uniform temperature load, which usually does not reflect the real case. Similarly, Lee et al [26], [27] investigated the equivalent structural properties of µ-bump surrounded by underfill, and applied it for the failure analysis of a chip stacking packaging. Thanks to the use of equivalent material properties, the numerical simulation of 3D ICs can be greatly simplified in terms of the modeling and solution process.…”

Section: Introductionmentioning

confidence: 99%

Coupled Thermo-Mechanical Analysis of 3D ICs Based on an Equivalent Modeling Methodology With Sub-Modeling

et al. 2020

View full text Add to dashboard Cite

The coupled thermo-mechanical field analysis of three-dimensional (3D) stacked integrated circuits (ICs) is evaluated by an efficient and accurate simulation strategy that combines equivalent homogenization modeling methodology and sub-modeling technique. The thermal field is first investigated using the proposed approach, and based on which the structural field is also examined through the calculation of warpage. The utilization of sub-modeling method reveals the local temperature and warpage distributions, which is lost or ignored by the conventional homogenization method. To validate the proposed method, the simulation results of a five-layer stacked integrated circuits are compared against true 3D results of the detailed model, where the maximum deviation for temperature and warpage is as low as 1.62% and 4.89%, respectively, which are greatly improved compared to 8.23% and 7.83% using traditional homogenization method. In addition, the total computation time is reduced by 76.7% in contrast to true 3D finite element analysis (FEA) simulation. Furthermore, the impacts of through-silicon-via (TSV) geometries, underfill and µ-bump parameters on the temperature and warpage distributions are also studied to guide the design of 3D ICs with high performance and reliability. INDEX TERMS Three-dimensional integrated circuits, coupled thermo-mechanical analysis, equivalent homogenization modeling, sub-modeling technique, through-silicon-via.

show abstract