Development of a high-yield via-last through silicon via process using notchless silicon etching and wet cleaning of the first metal layer

Watanabe, Naoya; Kikuchi, Hidekazu; Yanagisawa, Azusa; Shimamoto, H.; Kikuchi, Katsuya; Aoyagi, Masahiro; Nakamura, Akio

doi:10.7567/jjap.56.07ke02

Cited by 13 publications

(7 citation statements)

References 22 publications

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“…The leakage current between TSV-bump pairs was 2.1 pA at 5 V, which was sufficiently small for practical applications. Moreover, breakdown did not occur even at 40 V. Considering our previous data where breakdown of the TSV liner oxide occurred at 3 V when notching size was large (approximately 1.4 μm), 17) we can conclude that the result of the two-terminal measurement is good and primarily due to the effect of notchless Si etching.…”

Section: Electrical Characterization Of Stacked Chipsmentioning

confidence: 47%

“…To overcome these problems, we proposed a novel via-last TSV process using notchless Si etching and wet cleaning of the first metal layer. [15][16][17] In this process, the notching was suppressed by optimizing the deep Si etching conditions. In addition, wet cleaning of the first metal layer was performed with an organic alkaline solution to remove the contaminants and create good electrical contact between the TSV and first metal layer.…”

Section: Introductionmentioning

confidence: 99%

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Fabrication and stacking of through-silicon-via array chip formed by notchless Si etching and wet cleaning of first metal layer

Watanabe

Kikuchi²,

Yanagisawa³

et al. 2019

Jpn. J. Appl. Phys.

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We combined a "via-last through-silicon via (TSV) process consisting of notchless Si etching and wet cleaning of the first metal layer" with the solder bonding process using Ar fast atom beam (FAB), and realized the fabrication and three-dimensional (3D) stacking of a high-density TSV array chip. The size of the TSV array was 76 × 500. The diameter and length of the TSV were 6 and 21-22 μm, respectively. As the TSV array chip was very thin (approximately 26 μm) and had a strip-like shape, it was fragile and warped by approximately 90 μm. Hence, an electrostatic chuck was introduced and the TSV array chip was stacked by using a soft material (Cu-Ni-Sn based solder) as a bump and performing low-pressing-load low-temperature bonding with Ar FAB. As a result, the warpage of TSV array chip was suppressed and the TSV array chip was stacked without causing damage to the TSV and Si region. In addition, it was confirmed that the (i) leakage current between TSV-bump pairs is small, (ii) multilayer wiring + TSV + bump connection exhibit low resistance, and (iii) daisy chain is perfectly connected to up to 38 000 TSVs. These results are due to the effects of notchless Si etching, wet cleaning of the first metal layer, introduction of an electrostatic chuck, low-pressing-load low-temperature bonding with a soft material, and Ar FAB. This process will facilitate the development of face-up type 3D stacked sensor systems.

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Section: Electrical Characterization Of Stacked Chipsmentioning

confidence: 47%

Section: Introductionmentioning

confidence: 99%

Fabrication and stacking of through-silicon-via array chip formed by notchless Si etching and wet cleaning of first metal layer

Watanabe

Kikuchi²,

Yanagisawa³

et al. 2019

Jpn. J. Appl. Phys.

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“…While, TSV technology have been available for a long time, distinct constraints of materials and methods used in MEMS fabrication processes lead to different requirements and production flows. Via last approach offers design flexibility [1] however, it is not applicable when there are suspended structures or temperature sensitive materials that are common in MEMS technology. For MEMS fabrication flows, via first approach can be adopted, where TSV is prepared at the beginning of the process flow.…”

Section: Introductionmentioning

confidence: 99%

“…In the FLAMENCO 1 Project, a multi-chip system for fully implantable cochlear implants (FICI), consisting of energy harvester and transducer chips are produced [2], [3]. Resonator chip package needs to be below 20 mg, to prevent damage to the resonating body in the inner ear where it is attached, and increased weight may damage and suppress the movement of the ossicles or tympanic membrane [4].…”

Section: Introductionmentioning

confidence: 99%

Fabrication and Feasibility of Through Silicon Via for 3D MEMS Resonator Integration

et al. 2019

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In this study, development of a wafer level, void free TSV fabrication process flow and feasibility study of TSV integration to MEMS piezoelectric resonator devices have been presented. TSV structures with 100 µm diameter and 350 µm depth were copper filled with via sealing and bottom-up electroplating process which is a two-step technique. Four-point Kelvin measurements showed 0.8 mΩ TSV resistance on fabricated TSVs. Furthermore, TSV frames were epoxy bonded to MEMS acoustic transducers, which showed 90% to the resonator signal from the TSV.

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“…Moreover, the TSV manufacturing costs for 3D integration is high due to limited yield rate. For example, an 83% yield rate with state-of-the-art manufacturing for an 8-inch wafer is considered as the bestachieved rate for TSV-based ICs (Lau 2010;Watanabe et al 2016Watanabe et al , 2017. On the other hand, the direct wafer-bonding technique in M3D does not face such difficulties, and hence, achieves high yield and low cost (Batude et al 2012;Uhrmann et al 2014).…”

mentioning

confidence: 99%

Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-Chip

Das

Doppa

Pande

et al. 2018

ACM Trans. Des. Autom. Electron. Syst.

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Three-dimensional (3D) integration enables the design of high-performance and energy-efficient network on chip (NoC) architectures as communication backbones for manycore chips. To exploit the benefits of the vertical dimension of 3D integration, through-silicon-via (TSV) has been predominantly used in state-of-the-art manycore chip design. However, for TSV-based systems, high power density and the resultant thermal hotspot remain major concerns from the perspectives of chip functionality and overall reliability. The power consumption and thermal profiles of 3D NoCs can be improved by incorporating a Voltage-Frequency-Island (VFI)-based power management strategy. However, due to inherent thermal constraints of a TSV-based 3D system, we are unable to fully exploit the benefits offered by the power management methodology. In this context, emergence of monolithic 3D (M3D) integration has opened up new possibility of designing ultra-low-power and high-performance circuits and systems. The smaller dimensions of the inter-layer dielectric (ILD) and monolithic inter-tier vias (MIVs) offer high-density integration, flexibility of partitioning logic blocks across multiple tiers, and significant reduction of total wire-length. In this work, we present the first-ever study of the performance-thermal tradeoffs for energy efficient monolithic 3D manycore chips. In particular, we present a comparative performance evaluation of M3D NoCs with respect to their conventional TSV-based counterparts. We demonstrate that the proposed M3D-based NoC architecture incorporating VFI-based power management achieves a maximum of 29.4% lower energy-delay-product (EDP) compared to the TSV-based designs for a large set of benchmarks. We also demonstrate that the M3D-based NoC shows up to 29.1% lower maximum temperature than the TSV-based counterpart for these benchmarks.

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Development of a high-yield via-last through silicon via process using notchless silicon etching and wet cleaning of the first metal layer

Cited by 13 publications

References 22 publications

Fabrication and stacking of through-silicon-via array chip formed by notchless Si etching and wet cleaning of first metal layer

Fabrication and stacking of through-silicon-via array chip formed by notchless Si etching and wet cleaning of first metal layer

Fabrication and Feasibility of Through Silicon Via for 3D MEMS Resonator Integration

Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-Chip

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