Development of a low-power SRAM compiler

Abstract

i $EVWUDFWConsiderable attention has been paid to the design of low-power, highperformance SRAMs (Static Random Access Memories) since they are a critical component in both hand-held devices and high-performance processors. A key in improving the performance of the system is to use an optimum sized SRAM.In this thesis, an SRAM compiler has been developed for the automatic layout of memory elements in the ASIC environment. The compiler generates an SRAM layout based on a given SRAM size, input by the user, with the option of choosing between fast vs. low-power SRAM. Array partitioning is used to partition the SRAM into blocks in order to reduce the total power consumption.Experimental results show that the low-power SRAM is capable of functioning at a minimum operating voltage of 2.1 V and dissipates 17.4 mW of average power at 20MHz. In this report, we discuss the implementation of the SRAM compiler from the basic component to the top-level SKILL code functions, as well as simulation results and discussion.ii With the increasing use of portable consumer electronics, power consumption has become an important performance characteristic for a chip due to both limited battery life in portable systems and also due to expensive packages and heat sinks required by high power levels. Consequently, the design of low-power digital systems is becoming increasingly important. With memories typically accounting for the largest share of power consumption in a system, an emphasis has been placed on the design of low-power memories.More than half of the transistors in today's high performance microprocessors are devoted to cache memories and this ratio is expected to increase in the foreseeable future.Typically, SRAM (Static Random Access Memory) is the choice for embedded memories as SRAM is robust to the noisy environment in such chips. As a result, considerable attention has been paid to the design of low-power, high-performance SRAMs since they are a critical component in both hand-held devices and high-performance processors.A key in improving the performance of the system is to use an optimum sized SRAM. By incorporating an SRAM that is the correct size for the system requirements, the system can avoid using unnecessary memory cells. This leads to improvements in area, speed, and power. Therefore, depending on the application's need, an appropriate SRAM size should be used.In this thesis, an SRAM compiler has been developed for the automatic layout of memory elements in the ASIC environment. The compiler will generate an SRAM layout based on a given SRAM size, input by the user. Also, the compiler allows the user to choose between fast vs. low-power SRAM. The SRAM memory array is partitioned into blocks in order to reduce the total power consumption. The Cadence design environment is used for this thesis. Cadence SKILL language is used to implement the compiler and Cadence Virtuoso is used for the layout-editor tool.The organization of the thesis is as follows. In Chapter 2, the background related to the the...

Performance Analysis of 9T SRAM using 180nm, 90nm, 65nm, 32nm, 14nm CMOS Technologies

“…3. When compared to a simple 6T SRAM cell developed at the same technology, the proposed design has a 22% reduction in static power dissipation.…”

“…In comparison to the various 9T SRAM CMOS technology at different scaling node offers all data isolation by the bit lines of the memory cell, preventing sneak path, enabling higher data read and write stability, as well as lower leakage power. The SRAM cell of 9T is analyzed and carried out for its several parameters such as delay, power, voltage and temperature [3][4][5]. The CMOS based SRAM cell design having less power consumption.…”

CMOS VLSI subsystems for low-voltage low-power applications

“…As mentioned earlier, power-efficient SRAM is the heartland of our technology savvy mass market, which serves as a viable contender for cache memories [124][125][126]. Its memory capacities have been quadrupling from one generation to another almost every three-yearly [107].…”

SRAM Compiler For Automated Memory Layout Supporting Multiple Transistor Process Technologies

“…A user will specify how large of a memory is needed, what kind of memory, and often other features such as an optimization for speed, power, or area, an option to choose the desired aspect ratio of the cell, and more. An SRAM cell layout is used as the "leaf cell" [13] which is copied numerous times to form an array (core block), and then external circuitry such as an address decoder, precharge circuits, and sense amplifiers are added to the peripherals of the core memory block. Designing an integrated circuit requires several software tools.…”