Development of Cryogenic Readout Electronics for Far-Infrared Astronomical Focal Plane Array

Abstract

SUMMARYWe have been developing low power cryogenic readout electronics for space borne large format far-infrared image sensors. As the circuit elements, a fully-depleted-silicon-on-insulator (FD-SOI) CMOS process was adopted because they keep good static performance even at 4.2 K where where various anomalous behaviors are seen for other types of CMOS transistors. We have designed and fabricated several test circuits with the FD-SOI CMOS process and confirmed that an operational amplifier successfully works with an open loop gain over 1000 and with a power consumption around 1.3 μW as designed, and the basic digital circuits worked well. These results prove that the FD-SOI CMOS process is a promising candidate of the ideal cryogenic readout electronics for farinfrared astronomical focal plane array sensors.

Development of Low Power Cryogenic Readout Integrated Circuits Using Fully-Depleted-Silicon-on-Insulator CMOS Technology for Far-Infrared Image Sensors

“…The result of characterization at 4 K is summarized in Table 2. The detail of the measurement is described in the other paper [14].…”

“…Because the ST FD-SOI FETs show excellent cryogenic performance both for n-channel and p-channel, we can take advantage of well established standard CMOS circuit technologies. Using this process, we have fabricated two chips, one in 2008 which contains basic analog circuits including operational amplifiers (OP-AMP) and an off-resistance evaluation circuit; another chip, developed in 2009, contains basic analog-digital circuits including analog-to-digital converter and digital-to-analog converter [14], in order to verify the capability of the FD-SOI-CMOS for the ROIC of the far-infrared imaging sensors.…”

Development for Germanium Blocked Impurity Band Far-Infrared Image Sensors with Fully-Depleted Silicon-On-Insulator CMOS Readout Integrated Circuit

“…We fabricated CMOS OPAMP and confirmed superior performance compared with that of PMOS OPAMP [17][18][19], and have successfully demonstrated a capacitive transimpedance amplifier (CTIA) at 4.2 K with 1 µW power consumption. We measured the off-leakage current of an NMOS FET reset switch with a gate width/length ratio (W/L) of W/L = 5 µm/10 µm at 4.2 K and that was less than 1.5 × 10 −16 A with |V DS | ∼ 1 V [18].…”

Linearization Technique of Low Power Opamps in CMOS FD-SOI Technologies

“…In comparison with the mainstream bulk CMOS, CMOS FD-SOI technology [1,2] provides a set of benefits for analog circuits, such as better transconductance efficiency (g m /I D ), higher bandwidth (f T and f max ), better matching, and lower subthreshold leakage. It has also been demonstrated that FD-SOI CMOS can be a technology of choice for cryogenic integrated circuits [3,4]. However, a really unique feature of FD-SOI MOS devices is that they are double-gate transistors.…”