Development of layout split algorithms and printability evaluation for double patterning technology

Chiou, Tsann-Bim; Socha, Robert; Chen, Hong; Chen, Luoqi; Hsu, Stephen; Nikolsky, Peter; Oosten, Anton van; Chen, Alek C.

doi:10.1117/12.773107

Cited by 29 publications

(32 citation statements)

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“…To overcome this NC, the wire w 1 on the metal-2 layer is moved leftward. Thus, the odd cycle is eliminated because the right end of w 2 is shortened and separated from w 4 .…”

Section: B Dpt-compliant Redesignmentioning

confidence: 99%

“…Chiou et al [4] proposed a rule-based approach for pattern decomposition, which first pre-fragments the patterns and then iteratively colors the polygons in a greedy manner. Kahng et al [15] presented a decomposition flow with conflict graph construction, node splitting, and integer linear programming (ILP) optimization.…”

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confidence: 99%

“…For example, from the results of decomposition, Oosten et al [18] found that NCs may occur, which prohibits the existence of a DPT solution by any approach, even manually. Chiou et al [4] also stated that the unresolvable conflicts require modifications in the design to achieve a DPTcompliance design. Therefore, dealing with the NC problem is a crucial part of implementing the DPT process.…”

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confidence: 99%

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Native-Conflict and Stitch-Aware Wire Perturbation for Double Patterning Technology

Fang

Chen

Chang

2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Double patterning technology (DPT), in which a dense layout pattern is decomposed into two separate masks to relax its pitch, is the most popular lithography solution for the sub-22 nm node to enhance pattern printability. Previous work focused on stitch insertion to improve the decomposition success rate. However, there exist native conflicts (NCs) which cannot be resolved by any kind of stitch insertion. A design with NCs is not DPT-compliant and may fail the decomposition, resulting in design for manufacturability redesign and longer design cycles. In this paper, we give a sufficient condition for the NC existence and propose a geometry-based method for NC prediction to develop an early-stage analyzer for DPT decomposability checking. Then, a wire perturbation algorithm is presented to fix as many NCs in the layout as possible. The algorithm is based on iterative 1-D compaction and can easily be embedded into existing industrial compaction systems. The algorithm is then further applied to further reduce the number of stitches required for the decomposition process. Experimental results show that the proposed algorithm can significantly reduce the number of NCs by an average of 85% and reduce the number of stitches by an average of 39%, which may effectively increase the decomposition success rate for the next stage.

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“…To overcome this NC, the wire w 1 on the metal-2 layer is moved leftward. Thus, the odd cycle is eliminated because the right end of w 2 is shortened and separated from w 4 .…”

Section: B Dpt-compliant Redesignmentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

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Native-Conflict and Stitch-Aware Wire Perturbation for Double Patterning Technology

Fang

Chen

Chang

2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Conventional layout decomposition algorithms 2,3,8 focus on solving the color assignment problem, and ignore the impact of stitches on circuit performance. Yang et al 12 propose a multi-objective layout decomposition framework that accounts for circuit timing.…”

Section: Introductionmentioning

confidence: 99%

Performance and variability driven guidelines for BEOL layout decomposition with LELE double patterning

2011

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Litho-etch-litho-etch (LELE) double patterning lithography (DPL) is a strong candidate for BEOL patterning at the 20nm logic half-node (sub-80nm pitch). In double patterning lithography, layout pattern features must be assigned opposite colors if their spacing is less than the minimum coloring spacing. However, complex layouts usually have features that are separated by less than the minimum coloring spacing for any coloring assignment. To resolve the minimum coloring spacing constraint, a pattern feature (polygon) can be split into two different-color segments, introducing a stitch at the splitting location. Although many DPL layout decomposition heuristics have been proposed, the impact of stitches on circuit performance is not clearly analyzed. In this work, we study the impact of stitches on BEOL electrical performance based on analytical RC equations. Our studies with 45nm (commercial) and 22nm (ITRS) technology parameters show that (1) optimal stitching location can reduce delay variation by 5%, and (2) introducing redundant stitches (i.e., splitting an interconnect segment intentionally) can potentially reduce circuit delay variation.

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“…A lot of previous DPL decomposers simply ignore DPL incompatibility [7] [8] [9] [14]. Kahng et al [9] use iterative searching of odd cycles and generate candidate stitches heuristically.…”

Section: Introductionmentioning

confidence: 99%

A matching based decomposer for double patterning lithography

Chu

2010

Proceedings of the 19th International Symposium on Physical Design

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Double Patterning Lithography (DPL) is one of the few hopeful candidate solutions for the lithography for CMOS process beyond 45nm. DPL assigns the patterns less than a certain distance from each other on each layer onto two masks instead of one mask in traditional lithography. In this paper, we prove that the conflict graph used to model DPL conflicts in layout is a planar graph. Based on the planarity of the conflict graph, we propose a new face merging based framework which formulates DPL decomposition as a problem of pairing odd faces to simultaneously minimize the number of stitches generated and conflicts to eliminate. We employ partitioning and simplification techniques to reduce the problem size and use an O(n 3 ) time maximum weighted matching algorithm to generate an optimal DPL decomposition.

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Development of layout split algorithms and printability evaluation for double patterning technology

Cited by 29 publications

References 0 publications

Native-Conflict and Stitch-Aware Wire Perturbation for Double Patterning Technology

Native-Conflict and Stitch-Aware Wire Perturbation for Double Patterning Technology

Performance and variability driven guidelines for BEOL layout decomposition with LELE double patterning

A matching based decomposer for double patterning lithography

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